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Table of Content

    20 July 2014, Volume 50 Issue 4
    A 0.13-μm CMOS 6.25-Gb/s High-Speed Serial-Link Receiver
    LI Lu,WANG Zinan,GAI Weixin
    2014, 50(4):  617-622. 
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    A 0.13-μm CMOS 6.25-Gb/s high-speed serial-link receiver is designed. The receiver, using half-speed structure, consists of analog equalizer, sampler and DEMUX with required clock signal supplied by PLL and CDR block. A novel analogue equalizer with differential active inductor (DAL) is proposed to boost high-frequency gain and expand bandwidth. The DAL, only consisting of 4 NMOSs, saves large chip area and power consumption compared with other equivalent approaches. The DEMUX, adopting tree-type structure, is based on a novel 1:2 DEMUX unit, which saves 40% transistors compared with conventional equivalent. Simulation results with HSPICE show that the receiver works correctly in the condition of temperature range from ?55 to 125 °C, main process corner and 10% variation of voltage supply, and only consumes 3.6 mW power.
    Investigation of Hot Carrier Stress-Induced Degradation on SOI High Voltage Devices
    HAN Lin,HE Yandong,ZHANG Ganggang
    2014, 50(4):  632-636. 
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    A multi-region trap characterization direct current current-voltage (MR-DCIV) technique was proposed to characterize interface state generation from the channel to STI drift region. Degradation of STI-based LDMOS transistors in various hot-carrier stress modes is investigated experimentally by MR-DCIV technique. The impact of interface state location on device electrical characteristics is analyzed. The result reveals that the maximum Isub stress becomes the worst degradation mode in term of the on-resistance degradation, and the dominant degradation mechanism under hot-carrier stress is different from the conventional MOSFETs.
    Study on Temperature Control System Based on a MEMS Heater
    JIANG Shaobo,SU Weiguo,WAN Song,DENG Kangfa,ZHANG Wei
    2014, 50(4):  623-626. 
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    The authors present a temperature control system based on a MEMS heater. The MEMS heater has the advantages of high heating efficiency (7.35 mm2K/mW) and low power consumption. Besides, it has a high degree of system integration (6 mm ×6 mm). Fuzzy-PID control method that takes fuzzy adjustment to the PID parameters is used. The temperature control system achieves a high control accuracy of less than 0.1oC and a quick response time of about 10 s. With a MEMS pressure sensor, this system greatly suppresses the temperature drift.
    A Low-Power AGC for BD-II/GPS Receiver
    HOU Zhongyuan,LIU Junhua,LIAO Huailin,ZHANG Xing
    2014, 50(4):  627-631. 
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    A low-power automatic gain control (AGC) strategy for BD-II/GPS compatible satellite navigation receivers is proposed. The proposed mixed-signal AGC has 55 dB gain control range and a simplified control loop. By monitoring the ADC sampling result, the proposed AGC automatically controlvariable gain amplifier (VGA) and programmable gain amplifiers (PGA). Compared with traditional counterpart, the proposed AGC strategy is more power-efficient, since it does not need a power detector or rectifier. The chip is fabricated in a TSMC 0.18 μm CMOS process and the measure results show that the settling time of AGC is within 1 ms, and it consumes only 2 mA current at 1.8 V power supply.
    Correlation Electromagnetic Analysis Attacks against an FPGA Implementation of AES
    ZHANG Xiao,CUI Xiaoxin,WEI Wei,HUANG Ying,LIAO Kai,LIAO Nan,YU Dunshan
    2014, 50(4):  647-651. 
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    To study the vulnerability of Advanced Encryption Standard (AES) against electromagnetic side channel attacks, based on the method of correlation electromagnetic analysis (CEMA) attack, the authors built a platform to acquire EM emanation and process data, then performed a near-field CEMA attack against an FPGA implementation of AES-128. The results indicate that the platform is able to acquire the EM emanation of the encryption chip, and can retrieve all the 16 bytes of the 10th roundkey of AES. After the optimization of processing data, the efficiency of CEMA is highly enhanced, namely the data needed to exploit the correct roundkey is greatly reduced.
    Research on DPA Resistant Circuit for FPGA
    HUANG Ying,CUI Xiaoxin,WEI Wei,ZHANG Xiao,LIAO Kai,LIAO Nan,YU Dunshan
    2014, 50(4):  652-656. 
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    The authors studied the DPA attack method and circuit level protection technology, and introduced a security circuit WDDL on FPGA and a new symmetrical routing technology. A 4-bit WDDL adder on FPGA (field programmable gate array) platform was implemented and the power consumption of the circuit was analyzed. The results show that power consumption of WDDL decreases obviously than that of the traditional circuit and WDDL circuit can reduce the correlation of power consumption and data effectively. WDDL is proved to have better anti DPA (differential power analysis) attack ability at the cost of chip size.
    Fast Pre-charge Sense Amplifier for Low-Voltage Flash Memory
    HUANG Peng,WANG Yuan,DU Gang,ZHANG Ganggang,KANG Jinfeng
    2014, 50(4):  600-604. 
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    A new flash sense amplifier (SA) is presented, which has a fast pre-charge speed, low power and low supply voltage. Compared to the conventional low-voltage SA, the novel amplifier uses two inverters to improve pre-charge speed by feedback-control pre-charge circuit and to reduce power consumption by taking place of the current source module in reference voltage generation circuit, respectively. In 65 nm CMOS process, the pre-charge time of novel circuit is improved above 15%, and the power dissipation is lowered about 14%.
    A Novel Algorithm to Evaluate the Gain of DCO in ADPLL
    WU Bohan,GAI Weixin
    2014, 50(4):  611-616. 
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    A novel algorithm of evaluating the gain of DCO in all digital PLL (ADPLL) is proposed. It utilizes the digital information in ADPLL and evaluates the gain of DCO by calculating the variation of phase error, frequency error and the oscillator tuning word. As a result, the ADPLL is more immune to the environment. This algorithm is suitable for all counter-assistant ADPLLs, and it can work well in the type-II, 2rd order ADPLL, which is widely used in wireless communications.
    Novel Ultra-Low-Leakage ESD Power Clamp Circuit in Nanoscale Process
    WANG Yuan,ZHANG Xuelin,CAO Jian,LU Guangyi,JIA Song,ZHANG Ganggang
    2014, 50(4):  595-599. 
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    A novel electrostatic discharge (ESD) power clamp circuit with ultra-low leakage current is proposed. An ESD transient detective circuit with feedback loop is used to reduce the voltage between the bulk and gate of MOS capacitor, which results in a ultra-low leakage current performance of novel circuit. Verified by HSPICE simulation in 65 nm CMOS process, the standby leakage current of novel circuit is 24.13 nA, which is more than two-orders lower than that of the traditional design about 5.42 μA.
    Volumetric Display System Based on FPGA and DLP Technologies
    CAO Jian,JIAO Hai,WANG Yuan,ZHANG Xing
    2014, 50(4):  605-610. 
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    A volumetric display system based on FPGA and DLP technologies is raised. FPGA is used to construct the graphical processing unit, controlling and propagating video streams synthesized after image dithering and layer combined algorithms. This video stream is passed down inside the FPGA through SD card controlling unit, DDR2 high speed memory control, pixel frame converter and HDMI high resolution signal transmitting modules. Afterwards, the video stream is captured by the receiving end of the DLP projector, inside the projector’s video decoding module, the digital electrical signal is converted to light signal and projected to a spinning display underneath. This method allows the viewer perceiving a multi-angled 3D image hovering in air without the wearing of special glasses.
    Experimental Study on Positive Bias Temperature Instability of SOI nMOSFETs with High-k Gate Dielectrics
    LI Zhe,Lü Yinxuan,HE Yandong,ZHANG Ganggang
    2014, 50(4):  637-641. 
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    Experimental study on the positive bias temperature instability (PBTI) degradation and recovery of SOI nMOSFET with high-k gate dielectrics was conducted with comparison of negative bias temperature instability (NBTI) in pMOSFETs. A comprehensive analysis was presented on impacts of PBTI in terms of threshold voltage shift(Vth), drain current in linear region (Idlin) and saturated region (Idsat), subthreshold swing (S) and stress-induced leakage current (SILC). The results show that the degradation and recovery of PBTI have the similar tendency as NBTI, but the higher degradation rate and lower recovery ratio than NBTI may produce an effect on the lifetime prediction. Interface traps and oxide traps generation under PBTI stress were investigated and their influences to the device degradation were also presented.
    Montgomery Multiplier Based on Secondary Booth Encoding in RSA Encryption
    WANG Tian,CUI Xiaoxin,LIAO Kai,LIAO Nan,HUANG Ying,ZHANG Xiao,YU Dunshan
    2014, 50(4):  642-646. 
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    The authors discuss the performance and area of different large-scale Booth multipliers with high radices used in Montgomery algorithm using secondary encoded scheme. The modular multiplication is implemented with SMIC 0.13μm technology at the frequency of 160 MHz and 125 MHz respectively based on the 128-bit multiplier and 256-bit multiplier with Booth 64, 128 and 256 encoding. Experiment result shows that the multiplier with Booth 64, 128 and 256 can achieve the same timing performance, while the area rises as radix rises due to the complexity in pre-computation and partial product generation.
    Efficient Implementation of Generalized Binary Hessian Curve Based Processor for RFID
    LIAO Kai,CUI Xiaoxin,LIAO Nan,WANG Tian,ZHANG Xiao,HUANG Ying,YU Dunshan
    2014, 50(4):  657-663. 
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    Radio frequency identification (RFID) suffers extremely limited chip area and energy resource. A novel elliptic curve cryptographic (ECC) processer based on generalized binary Hessian curve (GBHC) is designed and implemented. The authors employ Montgomery Ladder scalar-multiplication algorithm and optimized w-coordinate method for accelerating the computing timing, and well-design circular shift register (CSR) architecture and clock gating technology for reducing the consumption of area and energy. The results show that the proposed processer has fast computing speed, minimal chip area and ultra-low energy consumption, and is capable to resist some types of side channel attack (SCA) such as simple power analysis (SPA).
    Low Power Integrated Circuit Technologies in Wireless Sensor Networks
    HU Ziyi,ZHOU Yinhao,CHEN Lan,ZHANG Xu,WANG Teng,XIE Zheng
    2014, 50(4):  664-674. 
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    Base on traditional integrated circuit (IC) low power methods, the authors propose three low power technologies for further research and take an implementation of WSN sensor node as an example. At system level, the authors present an optimum scheme combined with compiling technology and a hardware structure which provides special low power modes for WSN. At circuit level, considering clock placement in arithmetic mapping phase, clock operators in collaboration with IC operator design methodology (ODM) is proposed. A low power design of WSN sensor node is implemented to verify the low power technologies presented above. The testing results show that WSN sensor node consumes 167 μW at chip level and PCB system 1.035 mW at PCB system level in deep sleep mode by the three methods.
    A Design of DES Encryption Chip with Resistance to Differential Power Analysis
    LI Rui,CUI Xiaoxin,WEI Wei,WU Di,LIAO Kai,LIAO Nan,MA Kaisheng,YU Dunshan
    2014, 50(4):  675-680. 
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    The authors propose a novel countermeasure which associates masking with RDI (random delay in- sertion). Further, multi-masking instead of transformed masking is proposed in order to defend DPA (differential power analysis) attack based on Hamming distance model. The combined countermeasure is implemented on Data Encryption Standard. The results show that combined countermeasure can defend DPA attack with 105 power traces, and increase 40% ability against DPA attack.
    A New High Speed Current Mode Sense Amplifier for Low Power SRAM
    TANG Wenyi,JIA Song,XU Heqing,MENG Qinglong,WANG Yuan,ZHANG Ganggang
    2014, 50(4):  681-684. 
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    A new fast and low power current mode SRAM (static random access memory) sense amplifier is proposed. The proposed SA (sense amplifier) is composed of two stages. It can amplify the signal to full swing fast by using a latch based high speed amplification stage. With the current conveyor, the novel SA cuts off the DC path, and therefore it reduces the DC power consumption. The simulation results show that the new SA can provide 17% improvement in the speed and consume 86% less energy than WTA sense amplifier, based on an industry standard 1.0 V/65 nm CMOS technology.
    A Single Device Clock Loaded Contention Constrained RAM Latch Design
    JIA Song,LIU Li,LI Tao,LI Xiayu,WANG Yuan,ZHANG Ganggang
    2014, 50(4):  685-689. 
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    A new structure of RAM type latch is proposed in which parallel charging branches are used to solve the contradiction of the switching current and the charging speed. Compared with the conventional structure, new latch can maintain a relatively high rate of charging and reduce the short-circuit power. Furthermore only one MOS transistor is needed as clock load, saving the power consumption of clocking. HSPICE simulation results show that the proposed RAM n-Latch and p-Latch exhibits 12.8% and 25.5% speed improvement, 19.8% and 26.9% PDP (power-delay product) reduction compared to reported structure.
    FPGA Implementation of Serial RapidIO Endpoint Controller Based on AXI Bus Interface
    CHEN Hongming,LI Lei,YAO Yiwu,ZHANG Wei,CHENG Yuhua,AN Huiyao
    2014, 50(4):  697-703. 
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    Aiming at the requirements of modern high performance embedded system with high speed Serial RapidIO (SRIO) interconnect, a SRIO protocol controller IP with AXI interface is proposed. The hardware design of SRIO IP is implemented on the Xilinx XC5VLX220-FF1760 FPGA device. The proposed SRIO IP implemented with reasonable hardware architecture and some key design thoughts, can improve the speed of information collection and the real-time quality of data transmission. Meanwhile, the SRIO IP with resort to AXI bus can be more easily integrated into an SoC chip, which can also provide higher bandwidth for data transmission inside the chip. Consequently, the multi-DSP inside the FPGA device with the proposed SRIO IP can stably work at a very high reading/writing rate of 3.125 Gbps for each channel, which shows the performance of the proposed SRIO IP.
    A Built-In Self-Test & Repair Scheme for TSV Interconnect in 3D ICs
    WANG Qiushi,TAN Xiaohui,GONG Haoran,FENG Jianhua
    2014, 50(4):  690-696. 
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    A built-in-self-test (BIST) & built-in-self-repair (BISR) scheme for detecting and repairing defective TSVs are proposed. The BIST circuit tests the TSVs, then the BISR circuit configures the TSV mapping logic according to the test result. The faulty TSV will be repaired by BISR circuit using TSV redundancy. The proposed design reduces the cost of TSV test, as well as mitigates the yield loss caused by TSV defects. Circuit simulations show that the area overhead and time overhead are acceptable.
    Studies on the Photoresponse in Graphene-Based Field-Effect Transistors
    WEI Zijun,WANG Zhigang,LI Chen,GUO Jian,REN Liming,ZHANG Zhaohui,FU Yunyi,HUANG Ru
    2014, 50(4):  704-708. 
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    Graphene-based field-effect transistors (FETs) were fabricated by electron beam lithography and lift-off process and the photoresponse in the transistor was investigated. Significant photocurrents can be detected when the channel graphene near the metal contact is illuminated by a laser spot (λ = 633 nm). Both the magnitude and direction of the photocurrent can be effectively modulated by the back-gate voltage. In addition, the photocurrent will saturate by increasing the gate voltage. A maximum responsivity of 46.5 μA/W is achieved, which can be contributed to develop the novel graphene-based photodetectors.
    A Built-In-Self Test Technique Based on Loopback for RF ICs
    CUI Wei,FENG Jianhua,YE Hongfei,YAN Peng
    2014, 50(4):  709-714. 
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    A BIST (built-in self-test) technique based on Loopback test is presented. A programmable CMOS attenuator for BIST based on Loopback is designed. The testing results of RF transceiver with BIST circuits indicate that this technique can correctly detect system fault, and can be used in product testing, reducing the testing time and testing cost.
    A Low-Noise CMOS Charge Readout ASIC for X-Ray Detectors
    WANG Qian,ZHANG Yacong,LU Wengao,SHEN Guangchong,CHEN Zhongjian,JIA Ruoxi
    2014, 50(4):  715-718. 
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    A 32-channel CMOS charge readout ASIC, which amplifies the weak signal generated by the X-ray detector array, is designed. Each channel contains a charge sensitive amplifier, a correlated double sampler, and a sample-and-hold circuit. Noise characteristic of the readout circuit, especially the CSA, is theoretically analyzed, based on which optimization of schematic is achieved. Simulation results show that the integrated output noise is 69.7 μV.
    A Hybrid Incremental and Cyclic ADC for IRFPA Readout Circuit
    FAN Miaomiao,ZHANG Yacong,LU Wengao,SHEN Guangchong,CHEN Zhongjian,MENG Xiangyun,LIU Sanlin
    2014, 50(4):  719-723. 
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    A 14-bit column-parallel hybrid incremental and cyclic ADC was designed for IRFPA (infrared focal plane array) readout circuit. The conversion consists of two steps which are incremental mode and cyclic mode. It is a good trade-off between resolution and conversion time. The circuit is implemented in XFAB 0.35 μm process with analog supply of 5 V and digital supply of 3.3 V. The converter is featured with a wide conversion range from 0 to 3.2 V. A conversion cycle needs 27.6 μs at clock frequency of 5 MHz for the 14-bit structure.
    A Novel Structure of ROIC for Pyroelectric Uncooled IRFPA
    WANG Guannan,LU Wengao,ZHOU Juanjuan,ZHANG Yacong,CHEN Zhongjian,JI Lijiu
    2014, 50(4):  724-728. 
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    The authors present a capacitive-transimpedance-amplifier (CTIA) structure which has a column-shared part for pyroelectric uncooled IRFPA (infrared focal plane array) to achieve high linearity, relatively low power, low noise and wide output range. This structure decreases the complexity of pixel circuit and obtains more design flexibility. To get continuous output, odd-even line alternate readout is adopted. A prototype chip using this architecture is designed with 0.35μm DPTM process. The power supply is 5 V, power consumption of CTIA in each column is about 29.3 μW and linearity is 99.98%. The prototype could be extended to 320×240 array.
    Improved Structure of Time-Divided Closed-Loop Accelerometer by Alternating the Voltage Biasing
    HUANG Jingqing,ZHAO Meng,ZHANG Tingting,CHEN Zhongjian,WU Feng,HONG Lichen,LIU Dahe,ZHANG Yacong,LU Wengao,GAO Chengchen,HAO Yilong
    2014, 50(4):  729-733. 
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    A new structure of time-divided closed-loop accelerometer is proposed. It requires only one operational amplifier as a negative-coefficient PID is just sufficient. This structure not only reduces the area consumption of the whole chip of the readout circuit, but also lowers the equivalent input noise acceleration as one operational amplifier and two large resistors are reduced. The readout circuit is fabricated using 0.35 μm HV CMOS process, with self-test function included. Test results show that the linearity of 99.72% is achieved under self-test mode. The root-mean-square output noise voltage is around 140 μV from DC to 200 Hz.
    A High-Resolution Analog Interface for Capacitive MEMS Gyroscope with Integrated SAR-ADC
    FANG Ran,LU Wengao,TAO Tingting,SHEN Guangchong,HU Junrong,CHEN Zhongjian,ZHANG Yacong,YU Dunshan
    2014, 50(4):  734-740. 
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    The authors present a drive and sense interface for MEMS vibratory gyroscopes. A gm-stage and a TIA are employed as the first stage to achieve low-noise C/V conversion. The signals of both drive mode and sense mode are converted to digital domain by integrated 1.25 MS/s 14-bit SAR-ADCs. With this strategy, the complexity of the analog circuit is reduced, and the signal in digital domain can be manipulated more accurately. The interface is applicable for the MEMS gyroscopes whose resonant frequency is from 3 kHz to 15 kHz. The circuit is designed in a 0.18μm CMOS process. Experimental results show that the capacitive noise density of the output is achieved to 0.03 aF/√Hz at 3.5 kHz.
    Investigations of Aluminum-Coated Silicon Wafer Bonding Using Tin as Intermediate Layer
    ZHU Zhiyuan,YU Min,HU Anqi,WANG Shaonan,MIAO Min,Chen Jing,JIN Yufeng
    2014, 50(4):  741-744. 
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    A method using tin as intermediate layer to bond aluminum-coated silicon wafers is researched. Compared with Al-Al direct thermo-compression bonding method, it provides a low temperature, low pressure and rapid wafer-bonding solution. The authors use 4-inch (100 mm) silicon wafers for the bonding experiment. A 500 nm-thick Al layer is sputtered onto the wafers. The wafers are then annealed in N2 ambient at 450°C for 30 minutes. Next, in situ Ar plasma sputter cleaning is performed followed by a 500 nm-thick tin layer deposition onto the aluminum layer. After that, the wafer pairs are loaded into a vacuum bonder. Average shear strength of 9.9 MPa is achieved after bonding for 3 minutes. With the increase of bonding time, the shear strength decreases significantly.
    Design of ESD Protection for Low Noise Amplifier through Matching Network
    YAN Wei,WANG Yuchen,WANG Zhenyu,SHI Guangyi
    2014, 50(4):  745-752. 
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    A low noise amplifier (LNA) for Beidou navigation system was designed through the standard GaAs pHEMT technology. This circuit had the operating frequency of 2.45 GHz and noise figure of 0.55 dB. ESD protection circuit was added through the input and output matching network. Finally ADS2011 was used to simulate the design. According to the comparison of the circuit with ESD protection and that without ESD protection, the conclusion can be drawn that the circuit with ESD protection will induce some decline of the performance, such as the gain drawn from 16 dB down to 15 dB, but the noise has no change; with the ESD protection, the circuit can be greatly improved in overall performance and robustness, and the circuit has good resistance to electrostatic interference.
    Design and Implementation of Baseband Transmitter for UHF RFID Reader
    YONG Shanshan,WANG Xin’an,ZHANG Fangni,SHI Xiaolong,LIU Bin,GUO Zhaoyang,Lü Wei,CAO Ying,SU Jiting
    2014, 50(4):  753-760. 
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    A baseband transmitter for UHF (ultra high frequency) RFID (radio frequency identification) reader is proposed, which supports ISO 18000-6B&6C protocol and works at 840-960 MHz. Taking security and compatibility into consideration, 2-bits PIE-kind encoder and PIE encoder are both implemented, the former is 6 times higher security than the later. In SSB modulation, when there is amplitude mismatch of two quadrature signals, it will generate two frequency bands and result in performance lost. For this problem, an amplitude matching module is integrated. A power adjustment module in baseband is also proposed to enhance the signal and get larger input signal for PA to generate larger PA output power. The whole reader chip is implemented in a 0.18μm CMOS process and consumes 209461 gates and 102.609 mW. The baseband transmitter takes up 22% of the total area. This novel architecture doesn’t bring much lost in area and power consumption compared with other existing designs.
    Reconfigurable Operators Array: Architecture and Modeling
    YONG Shanshan,WANG Xin’an,CAO Ying,ZHANG Fangni,SHI Xiaolong,XIE Zheng
    2014, 50(4):  761-767. 
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    A novel FPGA fabric, reconfigurable operators (ReOps) array, which can reduce configurable time greatly and obtain a comparable performance on speed, is composed of multiple kinds of ReOps which are coarse-grain and function changeable instead of fine-grain LUT (lookup table)-based CLBs (configurable logic blocks). ReOps are classified into four kinds, arithmetic ReOps, control ReOps, path ReOps and memory ReOps. The function set of ReOps is just like a set of instruction of circuit which is soundness for circuits’ implementation. A hierarchy interconnection architecture consists of global interconnection for performing long distance transfer, local interconnection for performing adjacent transfer and IO interconnection for performing system interface, is presented. The switch box is implemented by general switch array. Two kinds of segments are proposed, single line and group lines. The width of group lines is n (integer, n>1) bits which behaved consistently and can get a great reduction on configuration bit-stream and a better speed. In order to do deep research and analysis, a model of this fabric is also developed which can obtain a different fabric quickly with different architecture file.
    Low-Cost VLSI Implementation of Motion Estimation for H.264/AVC Encoders
    WANG Teng,WANG Xin’an,XIE Zheng,HU Ziyi
    2014, 50(4):  768-780. 
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    A pipelined architecture with novel memory structure is proposed with several modifications of the ME algorithm. Fast motion estimation with low hardware cost and less memory access is achieved by proper search strategy, efficient rate distortion optimization (RDO) cost calculation and interpolation components, innovative memory structure and optimized dataflow scheduling. The proposed design is synthesized by SMIC 130 nm CMOS technology process with a clock frequency of 167 MHz and consumes 181.7 K logic gates and 13.8 KB memory, which shows great hardware efficiency compared with other designs. The proposed design was finally integrated within an H.264/AVC encoder for FPGA prototyping and VLSI implementation. The core area of the overall chip is 1.74 mm×1.74 mm with SMIC 65 nm CMOS technology which can support real-time HD(1080P@60fps) encoding with a clock frequency of 350 MHz.
    Interface Defect Growth Model and Reliability Simulation of Charge Trapping Memory
    WANG Taihuan,LUN Zhiyuan,JIAO Yipeng,LIU Xiaoyan,DU Gang
    2014, 50(4):  781-785. 
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    The reliability simulation under the condition of different stress to charge trapping memory was performed by proposing a specific growth model of interface defect. It can provide a forecast of growth mechanism of interface defect and degeneration of device performance when charge trapping memory is under normal working condition.
    An Analytical Model of Gate-All-Around Nanowire Tunnel FET
    HE Yuan,WANG Juncheng,WEI Kangliang,LIU Xiaoyan
    2014, 50(4):  786-790. 
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    An analytical model for gate-all-around (GAA) nanowire tunnel FETs (TFET) is proposed. It proves that the TFETs have good performance in sub-threshold region. Research shows that the sub-threshold slop of GAA nanowire TFET is proportional to several model parameters, such as the diameter, the thickness of oxide layer, and the voltage of drain. The model and simulation would lay a good foundation for its future application in low-power circuits.