Abstract: A novel FPGA fabric, reconfigurable operators (ReOps) array, which can reduce configurable time greatly and obtain a comparable performance on speed, is composed of multiple kinds of ReOps which are coarse-grain and function changeable instead of fine-grain LUT (lookup table)-based CLBs (configurable logic blocks). ReOps are classified into four kinds, arithmetic ReOps, control ReOps, path ReOps and memory ReOps. The function set of ReOps is just like a set of instruction of circuit which is soundness for circuits’ implementation. A hierarchy interconnection architecture consists of global interconnection for performing long distance transfer, local interconnection for performing adjacent transfer and IO interconnection for performing system interface, is presented. The switch box is implemented by general switch array. Two kinds of segments are proposed, single line and group lines. The width of group lines is n (integer, n>1) bits which behaved consistently and can get a great reduction on configuration bit-stream and a better speed. In order to do deep research and analysis, a model of this fabric is also developed which can obtain a different fabric quickly with different architecture file.

Key words: FPGA, reconfigurable operators, architecture modeling, interconnection architecture

摘要： 提出一种由多种粗粒度、功能可配置的可重构算子组成的新型FPGA结构??可重构算子阵列结构, 能完全替代细粒度的基于查找表的可编程逻辑单元, 降低配置加载时间, 同时电路速度具有可比性。可重构算子分为运算类、控制类、路径类和存储类, 像电路指令集一样可支撑所有电路的实现。互连结构分为全局互连、局部互连和IO互连, 分别承载远距离、邻近和系统外部的数据传输, 互连开关采用通用开关阵列的形式。互连线段分为组线和单线两种, 其中组线的位宽大于1比特, 其行为一致, 从而减小开关数目, 提高传输速度。为了对该阵列结构进行性能分析和结构探索, 还针对该结构进行建模, 通过结构文件快速生成不同的结构, 可作为深入研究的有效手段。

关键词: FPGA, 可重构算子, 结构建模, 互连结构