To improve the efficiency of lattice-based cryptography in practical applications, the optimization technology of polynomial multiplication in lattice-based cryptography is proposed. The polynomial coefficients are stored in a ping-pong structure to improve the bandwidth. By eliminating pre-scale operations, 10.5% of modular multiplication operations and 16.7% of storage space are saved. The structure based on look-up table shift register and three-input adder is adopted to reduce the logical resource occupation. The pipeline structure with optional stages is designed to make the butterfly module in polynomial multiplication meet the timing requirements of different cryptographic hardware systems. The evaluation results show that the maximum frequency of low-area, balanced and high-performance implementations of the optimized butterfly unit can reach 150, 250 and 350 MHz, respectively. Compared with the existing implementation technologies, the optimized hardware implementation can achieve higher operating frequency with a smaller circuit area, which improves the efficiency of polynomial multiplication module by 22.8%. 

为提高格密码在实际应用中的运算效率, 提出一种格密码中多项式乘法运算的优化实现技术。该技术采用乒乓结构存储多项式系数, 用以提升存取带宽, 通过消除预缩放运算, 减少10.5%的模乘运算和16.7%的存储空间占用, 采用移位寄存器和三输入加法器的结构, 有效地减少逻辑资源占用。同时, 设计具有可选层级的流水线结构, 使多项式乘法中的蝶形运算模块可以满足不同密码硬件系统的时序要求。评估结果表明, 采用优化技术的低面积、均衡型和高性能实现的蝶形运算模块最大工作频率分别可达到150, 250和350 MHz以上。与现有实现技术相比, 优化的多项式乘法硬件实现能够以更小的电路面积实现更高的工作频率, 使电路效率提升22.8%。