Abstract: The authors discuss the performance and area of different large-scale Booth multipliers with high radices used in Montgomery algorithm using secondary encoded scheme. The modular multiplication is implemented with SMIC 0.13μm technology at the frequency of 160 MHz and 125 MHz respectively based on the 128-bit multiplier and 256-bit multiplier with Booth 64, 128 and 256 encoding. Experiment result shows that the multiplier with Booth 64, 128 and 256 can achieve the same timing performance, while the area rises as radix rises due to the complexity in pre-computation and partial product generation.

Key words: Montgomery multiplier, Booth’s algorithm, secondary Booth encoding scheme, Booth multiplier with high radix

摘要： 研究可用于Montgomery算法的基于二次编码的不同阶的Booth大数乘法器的性能和面积。 通过SMIC 0.13μm工艺实现的阶64, 128和256的128 bit和256 bit的Booth大数乘法器, 分别在160 MHz和125 MHz的频率下实现模乘运算。 实验结果表明, 阶64, 128和256的Booth乘法器在速度上性能一致, 但随着阶的增加, 由于预计算和产生部分积的复杂度上升, 乘法器的面积将增加。

关键词: Montgomery乘法器, Booth算法, 二次Booth编码, 高阶Booth乘法器