Abstract: Aiming at the requirements of modern high performance embedded system with high speed Serial RapidIO (SRIO) interconnect, a SRIO protocol controller IP with AXI interface is proposed. The hardware design of SRIO IP is implemented on the Xilinx XC5VLX220-FF1760 FPGA device. The proposed SRIO IP implemented with reasonable hardware architecture and some key design thoughts, can improve the speed of information collection and the real-time quality of data transmission. Meanwhile, the SRIO IP with resort to AXI bus can be more easily integrated into an SoC chip, which can also provide higher bandwidth for data transmission inside the chip. Consequently, the multi-DSP inside the FPGA device with the proposed SRIO IP can stably work at a very high reading/writing rate of 3.125 Gbps for each channel, which shows the performance of the proposed SRIO IP.

Key words: SRIO, AXI bus, PIPE, IP core

摘要： 针对现代高性能嵌入式系统高速串行RapidIO (SRIO)信号接入的应用需求, 提出一种基于AXI总线的SRIO端点控制器IP核设计方案。以XC5VLX220-FF1760现场可编程门阵列芯片为目标器件, 利用硬件设计实现SRIO接口电路。该方案采用合理的硬件结构, 能够提高信息采集和输出的时效性。此外, AXI总线能够使SRIO端点控制器IP核更方便地集成到SoC芯片中, 可以在片内提供更高的数据传输带宽。利用SRIO协议实现的FPGA内置多DSP IP核, 读写操作速率能稳定地达到每通道3.125 Gb/s, 表明所提出的IP具有高性能。

关键词: 串行RapidIO, AXI总线, PIPE, IP核