Abstract: A pipelined architecture with novel memory structure is proposed with several modifications of the ME algorithm. Fast motion estimation with low hardware cost and less memory access is achieved by proper search strategy, efficient rate distortion optimization (RDO) cost calculation and interpolation components, innovative memory structure and optimized dataflow scheduling. The proposed design is synthesized by SMIC 130 nm CMOS technology process with a clock frequency of 167 MHz and consumes 181.7 K logic gates and 13.8 KB memory, which shows great hardware efficiency compared with other designs. The proposed design was finally integrated within an H.264/AVC encoder for FPGA prototyping and VLSI implementation. The core area of the overall chip is 1.74 mm×1.74 mm with SMIC 65 nm CMOS technology which can support real-time HD(1080P@60fps) encoding with a clock frequency of 350 MHz.

Key words: H.264/AVC, motion estimation, pipeline architecture, real-time HD encoding, VLSI implementation

摘要： 通过对运动估计算法进行优化, 提出一种应用新型存储结构的流水线实现结构。通过采用合适的搜索策略、高效的率失真优化代价计算和插值部件、创新的存储结构及优化的数据流调度, 实现具有低硬件代价和存储访问的快速运动估计。该设计在SMIC 130 nm工艺下综合, 时钟频率可达到167 MHz, 消耗181.7 K逻辑门和13.8 KB存储, 相比同类设计具有更高的硬件效率。该设计集成在一个H.264/AVC编码器中进行FPGA原型验证和VLSI实现。 SMIC 65 nm工艺下, 整个芯片面积为1.74 mm×1.74 mm, 工作频率为350 MHz, 可以支持实时高清(1080P@60fps)编码。

关键词: H.264/AVC, 运动估计, 流水线结构, 实时高清编码, VLSI