Abstract: A 0.13-μm CMOS 6.25-Gb/s high-speed serial-link receiver is designed. The receiver, using half-speed structure, consists of analog equalizer, sampler and DEMUX with required clock signal supplied by PLL and CDR block. A novel analogue equalizer with differential active inductor (DAL) is proposed to boost high-frequency gain and expand bandwidth. The DAL, only consisting of 4 NMOSs, saves large chip area and power consumption compared with other equivalent approaches. The DEMUX, adopting tree-type structure, is based on a novel 1:2 DEMUX unit, which saves 40% transistors compared with conventional equivalent. Simulation results with HSPICE show that the receiver works correctly in the condition of temperature range from ?55 to 125 °C, main process corner and 10% variation of voltage supply, and only consumes 3.6 mW power.

Key words: serial-link receiver, equalizer, DEMUX

摘要： 基于1.2 V 0.13 μm CMOS工艺, 设计一种数据率为6.25 Gb/s的高速串行数据接收器。该接收器采用半速结构降低系统工作频率, 其中: 均衡电路利用一种低功耗小面积的差分有源电感, 使RC负反馈均衡电路的高频增益增加50%; 采样电路为半速时钟驱动2-way交织结构, 同时实现1:2串并转换功能; DEMUX采用树型(tree-type)结构, 并使用一种新的1:2 DEMUX单元, 较传统单元电路节省40%的晶体管数量。HSPICE仿真结果显示, 该接收器在?55~125℃温度范围、各主要工艺角及电源电压波动10%的条件下, 均能正确工作, 核心电路平均功耗为3.6 mW。

关键词: 串行接收器, 均衡器, 串并转换器