Acta Scientiarum Naturalium Universitatis Pekinensis ›› 2018, Vol. 54 ›› Issue (6): 1351-1354.DOI: 10.13209/j.0479-8023.2018.046

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Design and Implementation of an Asynchronous Low Power RSA Circuit Structure

ZHANG Qihui, CAO Jian, CAO Xixin, YU Dunshan, ZHANG Xing   

  1. School of Software and Microelectronics, Peking University, Beijing 102600
  • Received:2017-09-10 Revised:2017-10-17 Online:2018-11-20 Published:2018-11-20
  • Contact: ZHANG Xing, E-mail: zhx(at)


张奇惠, 曹健, 曹喜信, 于敦山, 张兴   

  1. 北京大学软件与微电子学院, 北京 102600
  • 通讯作者: 张兴, E-mail: zhx(at)


An asynchronous low power RSA circuit structure and its modular multiplication circuit structure for smart cards and RFID tags are proposed. By using GTECH optimization scheme and BrzCallMux implementation strategy, ASIC implementation is carried out based on a TSMC 130 nm standard CMOS technology. Experimental results show that the area of the proposed asynchronous low power RSA is only 4% of that of another asynchronous RSA, its average time to perform a cryptographic operation is only 0.216% of that of another asynchronous RSA, and its power consumption is only 16.99% of that of its corresponding synchronous counterpart.

Key words: asynchronous, low energy, RSA, GTECH, ASIC


提出一种适用于智能卡和电子标签的异步低功耗RSA电路结构及其模乘电路结构, 使用GTECH的优化方法和BrzCallMux的实现策略, 基于TSMC 130 nm CMOS标准工艺进行ASIC实现。结果表明, 所提出的异步低功耗RSA的面积最低仅为其他RSA面积的4%, 一次加解密时间最低仅为其他RSA加解密时间的0.216%, 功耗最低仅为其他RSA功耗的16.99%。

关键词: 异步, 低功耗, RSA, GTECH, ASIC

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