关键词: FPGA, 可重构算子, 结构建模, 互连结构

Abstract: A novel FPGA fabric, reconfigurable operators (ReOps) array, which can reduce configurable time greatly and obtain a comparable performance on speed, is composed of multiple kinds of ReOps which are coarse-grain and function changeable instead of fine-grain LUT (lookup table)-based CLBs (configurable logic blocks). ReOps are classified into four kinds, arithmetic ReOps, control ReOps, path ReOps and memory ReOps. The function set of ReOps is just like a set of instruction of circuit which is soundness for circuits’ implementation. A hierarchy interconnection architecture consists of global interconnection for performing long distance transfer, local interconnection for performing adjacent transfer and IO interconnection for performing system interface, is presented. The switch box is implemented by general switch array. Two kinds of segments are proposed, single line and group lines. The width of group lines is n (integer, n>1) bits which behaved consistently and can get a great reduction on configuration bit-stream and a better speed. In order to do deep research and analysis, a model of this fabric is also developed which can obtain a different fabric quickly with different architecture file.

Key words: FPGA, reconfigurable operators, architecture modeling, interconnection architecture