北京大学学报自然科学版 ›› 2021, Vol. 57 ›› Issue (5): 815-822.DOI: 10.13209/j.0479-8023.2021.039

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一种基于位线电荷循环的低功耗SRAM阵列设计

张瀚尊1, 贾嵩2,†, 杨建成1, 王源2   

  1. 1. 北京大学微电子学研究所, 北京 100871 2. 北京大学微电子器件与电路重点实验室, 北京 100871
  • 收稿日期:2020-07-08 修回日期:2020-12-16 出版日期:2021-09-20 发布日期:2021-09-20
  • 通讯作者: 贾嵩, E-mail: jias(at)pku.edu.cn

A Charge Recycling Scheme with Read and Write Assist for Low Power SRAM Design

ZHANG Hanzun1, JIA Song2,†, YANG Jiancheng1, WANG Yuan2   

  1. 1. Institute of Microelectronics, Peking University, Beijing 100871 2. Key Laboratory of Microelectronic Devices andCircuits, Peking University, Beijing 100871
  • Received:2020-07-08 Revised:2020-12-16 Online:2021-09-20 Published:2021-09-20
  • Contact: JIA Song, E-mail: jias(at)pku.edu.cn

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摘要：

为了降低静态随机存储器(SRAM)的动态功耗, 提出一种基于位线电荷循环的读写辅助电路的SRAM阵列。与传统设计性比, 辅助电路中转和保存了在读写操作中本该被直接泄放掉的位线电荷, 并重新用于下一个周期的位线充电。提出的SRAM存储器采用标准14 nm FinFET spice模型搭建, 电源供电电压为0.8 V。仿真结果表明, 与传统设计相比, 提出的存储阵列的功耗可以降低23％~43％, 并将SNM 和WNM至少提高25％和647.9％。

关键词: SRAM, 位线电荷循环, 读写辅助

Abstract:

In order to cut down the dynamic power of static random access memory (SRAM), a bitline charge cycling based read and write assist circuit for SRAM is presented. Compared with the traditional design, the assist circuit saves and reuses the bitline charge which should be directly discharged during read and write operation to reduce bitlines charging power consumption in the next cycle. The SRAM memory is built by the SMIC 14 nm FinFET spice model, and the power supply voltage is 0.8 V. The simulation results show that the power consumption of the proposed SRAM array is reduced by 23%–43% compared with the traditional design, and the SNM and WNM has increased by at least 25% and 647.9% respectively.

Key words: SRAM, bitline charge cycling, read and write assist

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