Abstract:

A mixed-monotonic capacitor switching scheme which can provide stable common-mode voltage (Vcm) without any additional voltage regulator and compensation capacitor array is proposed for the successive approximation register (SAR) analog-to-digital (ADC). The proposed scheme contains two equal amplitude but opposite monotonicity switched capacitor arrays, the stabilization of the common mode voltage is achieved with self-complementation of the differential voltage. Based on this technique, a 10-bit 50 MS/s prototype is designed in CMOS 0.18 μm technology. A window opening SAR logic is used to reduce the transmission time from the comparator out to DAC control signal. An adaptive delay chain is used in the comparator loop to reduce the conversion time of lower bit in the SAR ADC. Measurement result shows that the SAR ADC can achieve a SNDR equal to 57.31 dB, and INL and DNL are equal to 1.81 LSB and 0.98 LSB respectively.

Key words: mixed-monotonic capacitor switching, Vcm-stablized, SAR ADC

摘要：

提出一种应用于逐次逼近型模数转换器的混合电容切换模式。该模式包含两个幅度相同但单调性相反的开关电容阵列, 无需任何额外的稳压电源和电容补偿阵列, 通过差分电压自身的互相补偿, 实现共模电压的稳定。利用上述技术, 基于0.18 μm的CMOS工艺实现一个转换速率为50 MS/s, 分辨率为10-bit的SAR ADC。设计过程中采用开窗逻辑, 减小了比较器输出信号到DAC 控制信号的传输时间; 采用包含自适应延时逻辑的比较环路, 缩短了SAR ADC低位比特的转换时间。测试结果表明, 所设计的SAR ADC在50 MS/s 的转换速率下, 可以实现57.31 dB的SNDR, 1.81 LSB的INL以及0.98 LSB的DNL。

关键词: 混合电容切换, 共模稳定, SAR ADC