A mixed-monotonic capacitor switching scheme which can provide stable common-mode voltage (Vcm) without any additional voltage regulator and compensation capacitor array is proposed for the successive approximation register (SAR) analog-to-digital (ADC). The proposed scheme contains two equal amplitude but opposite monotonicity switched capacitor arrays, the stabilization of the common mode voltage is achieved with self-complementation of the differential voltage. Based on this technique, a 10-bit 50 MS/s prototype is designed in CMOS 0.18 μm technology. A window opening SAR logic is used to reduce the transmission time from the comparator out to DAC control signal. An adaptive delay chain is used in the comparator loop to reduce the conversion time of lower bit in the SAR ADC. Measurement result shows that the SAR ADC can achieve a SNDR equal to 57.31 dB, and INL and DNL are equal to 1.81 LSB and 0.98 LSB respectively.

%U https://xbna.pku.edu.cn/EN/10.13209/j.0479-8023.2018.048