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RiTLB: iTLB Design Based on Memory Region Reusing

XIE Jinsong, TONG Dong, LI Xianfeng, PANGJiufeng, WANG Keyi, CHENG Xu   

  1. Microprocessor Research and Development Center, Peking University, Beij ing 100871; , E-mail:
  • Received:2008-10-30 Online:2009-07-20 Published:2009-07-20

RiTLB: 基于存储区域重用的iTLB设计


  1. 北京大学微处理器研究开发中心, 北京100871,, E-mail:

Abstract: In order to design iTLB by memory region reusing, its comparison bits of lookup are reduced through the memory region encoding technology firstly, which encodes the higher-order bits of VPN with a very shorter memory region ID before the VPNis sent to iTLB. Secondly, the memory region IDis reused before the next memory region is switched into. Compared to the baseline iTLB, experimental results show the average dynamic power, delay and area of the new design decrease by 62.84%, 9.96% and 44.78% respectively, with only 0.23% average IPC reduction.

Key words: memory region, reusing, instruction translation lookaside buffer

摘要: 通过重用存储区域的标识设计iTLB。首先,将虚拟页号的高位编码成较短的存储区域标识,来减少iTLB查询时的比较位数。其次,在运行到新的存储区域之前,一直重用上次指令所在的存储区域的标识。实验结果表明,与参考iTLB 设计相比,这种存储区域重用的iTLB 设计技术,其平均功耗降低了62.84%,延迟减少了9.96%,面积减少了44.78%,而平均性能仅下降了0.23%。

关键词: 存储区域, 重用, 指令转换旁视缓冲

CLC Number: