北京大学学报自然科学版 ›› 2023, Vol. 59 ›› Issue (4): 555-562.DOI: 10.13209/j.0479-8023.2022.112

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一种高能效双发射处理器的设计与实现

张馨予1, 刘亮2, 王春萌1, 江凇3, 易江芳1,†   

  1. 1. 北京大学计算机学院系统结构研究所, 北京 100871 2. 北京智芯微电子科技有限公司 100192 3. 国网江苏省电力有限公司信息通信分公司, 南京 210000
  • 收稿日期:2022-07-12 修回日期:2022-10-28 出版日期:2023-07-20 发布日期:2023-07-20
  • 通讯作者: 易江芳, E-mail: yijiangfang(at)pku.edu.cn
  • 基金资助:
    国家电网总部科技项目(5700-202141449A-0-0-00)资助

Design and Implementation of an Energy Efficient Dual-Issue Processor

ZHANG Xinyu1, LIU Liang2, WANG Chunmeng1, JIANG Song3, YI Jiangfang1,†   

  1. 1. Institute of System Architecture, School of Computer Science, Peking University, Beijing 100871 2. Beijing Smart-Chip Microelectronics Technology Co., Ltd, Beijing 100192 3. STAET GRID Jiangsu Electric Power CO. LTD Information & Telecommunication Branch, Nanjing 210000
  • Received:2022-07-12 Revised:2022-10-28 Online:2023-07-20 Published:2023-07-20
  • Contact: YI Jiangfang, E-mail: yijiangfang(at)pku.edu.cn

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摘要：

为了提高高能效处理器的性能, 基于ECore嵌入式处理器平台, 在单反射按序流水线结构中引入两种轻量化的超标量结构——压缩指令双发射结构和选择性重命名结构。在Verilator生成的C++模型上进行的模拟实验结果表明, 通过增加压缩指令双发射结构, 流水线双发利用率平均值达到28%。通过增加选择性重命名结构, 因名称冒险导致的流水线停顿占比从7.2%降至0.6%。相对于优化前, 处理器的IPC提升4.8%, 而功耗仅增加2.5%。

关键词: 高能效处理器, 双发射, 寄存器重命名

Abstract:

In order to improve performance with stable power consumption, based on ECore embedded processor platform, which had a single-issue in-order pipeline structure originally, two lightweight superscalar structures were introduced: selective register renaming and dual issue of compact instructions. The experimental data showed that the average utilization of dual-issue structure reached 28% by adding dual issue logic. Using selective register renaming, the average stalling rate caused by name hazard reduced from 7.2% to 0.6%. Compared with the original design, the IPC increased 4.8% and the power consumption only increased 2.5%.

Key words: energy efficient processor, dual-issue, register renaming

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