北京大学学报(自然科学版)

适用于位交叉布局的低电压SRAM单元

贾嵩,徐鹤卿,王源,吴峰锋,李涛,徐越   

  1. 北京大学信息科学技术学院微电子系, 北京 100871;
  • 收稿日期:2012-05-24 出版日期:2013-07-20 发布日期:2013-07-20

Low Voltage SRAM Cell Suitable for Bit-Interleaved Structure

JIA Song, XU Heqing, WANG Yuan, WU Fengfeng, LI Tao, XU Yue   

  1. Key Laboratory of Microelectronics Devices and Circuits MOE, Department of Microelectronics, Peking University, Beijing 100871;
  • Received:2012-05-24 Online:2013-07-20 Published:2013-07-20

摘要: 提出一种9管单端SRAM单元结构, 该种SRAM单元采用读写分离方式, 具有较高的保持稳定性和读稳定性。 该单元采用新的写操作方式, 使由其组成的存储阵列中, 处于“假读”状态的单元仍具有较高的稳定性, 因此在布局时能够采用位交叉布局, 进而采用简单的错误纠正码(ECC)方式解决由软失效引起的多比特错误问题。仿真结果显示, 当电源电压为300 mV时, 该种结构的静态噪声容限为100 mV, 处于“假读”状态的单元静态噪声容限为70 mV。

关键词: SRAM单元, 低电压, 静态噪声容限, 位交叉结构

Abstract: A single-ended nine-transistor (9T) SRAM scheme is proposed for sub-threshold operation. The new SRAM cell provides high stability using disturb-free read operation. With a new write mechanism, the cell can solve the pseudo-read problem. Thus, the bit-interleaved structure can be used to address the multiple bit soft-errors problem. Simulation result shows that the SRAM cell can provide 100 mV read static-noise-margin (SNM) and 70 mV worst half-select SNM, when the supply voltage is 300 mV.

Key words: SRAM cell, low voltage, SNM, bit-interleaved structure

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