关键词: RapidIO, SRIO端点, 嵌入式互连, 串行物理层, 低时延

Abstract: A low latency endpoint implementation scheme compliant with specification V1.3 is described. A novel architecture is proposed where most modules in transmitting and receiving paths are designed to work in cut-through modes with the purpose of generating short and fixed latencies. To the transaction interface, requests and responses can be issued from different user-defined ports and sent through the proposed sharable transfer paths. Concurrent transactions can be kept in order by safety arbitration mechanisms. Furthermore, abandoned packets can be cancelled by the enhanced four-queue buffers to prevent invalid transmissions. To the 1x/4x serial physical interfaces, reliable transmissions of packets and control symbols are achieved. Crucial link managements including flow control, error detection and recovery are also supported. Compared with the reference designs, the proposed scheme can achieve lower latency and higher throughput performances. Furthermore, the feasibility and effectiveness have been confirmed by FPGA verifications. Therefore, this scheme is considered applicable in the next-generation high speed embedded interconnections.

Key words: RapidIO, SRIO endpoint, embedded interconnection, serial physical layer, low latency