关键词: 全球定位系统(GPS), 高灵敏度, 载波跟踪, 锁相环(PLL), 锁频环(FLL)

Abstract: This paper presents the design, optimization and implementation of GPS carrier tracking loop based on high sensitivity GPS base band signal processor research topic. The phase detector, loop error sources and loop parameters are first optimized to improve the tracking sensitivity and then the phase lock loop assisted by frequency lock loop circuit structure is applied. The circuit is optimized and timing-sharing technology is used for the modules including several multipliers and dividers to reduce resource consumption and save chip area. The authors implement the designed GPS carrier tracking loop in Verilog and complete the logic and functional simulation in Modelsim with RTL level code. The FPGA board verification platform is established and the performance test is carried out using GPS L1 band signal source. The test result shows that the tracking sensitivity can reach 25 dB-Hz and chip area of the single channel carrier tracking loop is 425555μm² in SMIC 0.18μm technology using Design Complier.

Key words: GPS, high sensitivity, carrier tracking, PLL, FLL