高灵敏度GPS接收机捕获电路的优化与实现

北京大学学报（自然科学版）

高灵敏度GPS接收机捕获电路的优化与实现

路卫军¹,黄永灿²,于敦山¹,张兴¹

1. 北京大学信息科学技术学院微电子研究所, 北京 100871; 2. 北京中微星通电子有限公司, 北京 100191;

收稿日期:2009-10-15 出版日期:2010-11-20 发布日期:2010-11-20

Acquisition Circuit for HSGPS Receivers: Optimization and Implementation

LU Weijun¹, HUANG Yongcan², YU Dunshan¹, ZHANG Xing¹

1. Deparment of Microelectronics, School of Information Science and Technology, Peking University, Beijing 100871; 2. Beijing Navichip Electronics Corp. Ltd, Beijing 100191;

Received:2009-10-15 Online:2010-11-20 Published:2010-11-20

摘要/Abstract

摘要： 基于传统的时域并行相关的能量检测技术提出一种资源优化方法, 通过两步相关法和分时共享技术进行相干积分, 对某一估计频率下的 1023 个不同的码相位进行并行处理, 在采样频率为 16. 368 MHz 的条件下所需相关器数量减少为未优化前的 1/ 102. 3。用 Verilog 硬件描述语言实现了采用优化技术的能量检测器, 给出了FPGA 实现结果和 Design Compiler 的综合结果。测试结果表明, 在预检测积分时间为 2s, C/N₀ = 21dB-Hz, 虚警概率为0. 097% 时, 捕获概率可达到90%。

关键词: 高灵敏度, 捕获电路实现, 全球定位系统

Abstract: The authors propose an optimizing method for the energy detector based on the parallel correlators in the time domain. With a method named as two-step correlation method and time sharing techniques, all the 1023 chip phases are detected in parallel. When the sampling frequency is 16. 368 MHz, the total correlator number is reduced to be 1/ 102. 3 of the non-optimized counterpart. Furthermore, the energy detector using the proposed method is implemented by FPGA and synthesized with Design Compiler. The test results show that when pre-detection time is 2s, C/N₀ = 21 dB-Hz, and false alarm is 0. 097% , the detection probability is as high as 90% .

Key words: high sensitivity, implementation of acquisition circuits, global positioning system

中图分类号:

TN46

路卫军,黄永灿,于敦山,张兴. 高灵敏度GPS接收机捕获电路的优化与实现[J]. 北京大学学报（自然科学版）.

LU Weijun,HUANG Yongcan,YU Dunshan,ZHANG Xing. Acquisition Circuit for HSGPS Receivers: Optimization and Implementation[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.

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