标准单元库版图缩放设计与实现

北京大学学报（自然科学版）

标准单元库版图缩放设计与实现

吴迪¹,马亮²,刘晓彦³

1.北京大学深圳研究生院，深圳518055；2.北京芯慧同用微电子技术有限公司，北京100083；3.北京大学微电子学系，北京100871；

收稿日期:2008-04-03 出版日期:2009-03-20 发布日期:2009-03-20

Design and Implementation of SCL Layout Scaling

WU Di¹， MA Liang², LIU Xiaoyan³

1. Shenzhen Graduate School，Peking University，Beijing 518055； 2. Vivace Semiconductor Beijing LTD，Beijing 100083；3. Department of Microelectronic，Peking University，Beijing 100871;

Received:2008-04-03 Online:2009-03-20 Published:2009-03-20

摘要/Abstract

摘要： 针对集成电路设计中IP硬核的复用设计了一套版图缩放流程。通过算法设计比例，编程自动识别、修改版图数据以及修正处理等一整套方法，使得版图数据可以灵活高效的缩小，复用到新工艺上。实验结果显示，该设计方法特别适用于标准单元库，有利于提高设计效率。

关键词: 版图缩放, 标准单元库, DRC

Abstract: A new set of scaling layout flow is presented to reuse IP hard core. The ratio design algorithm is developed to design scaled layout considering the relation of two different technology. Based on the ratio design algorithm, programmed data processing, the layout can be scaled appropriately and reused on the new technology nodes. Experiment proved the effectiveness of this method in use of SCL design and improvement of design efficiency.

Key words: layout scale, SCL, DRC

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