关键词: 并行BCH译码器, 判决树, 并行伴随式计算, 错误位置多项式

Abstract: A high speed VLSI decoder architecture is proposed for a standard forward error correction(FEC) in optical network. In the proposed parallel decoder architecture, a novel parallel computation of syndrome is presented to reduce the hardware complexity. A method is introduced to derive an inversion-free algorithm from the decision tree algorithm with the number of correctable errors less than 5. Area and timing estimates obtained by logic synthesis with 0.18 CMOS technology show that the implementation of (4359,4320)BCH (Bose-Chaud huri-Hocquenheim) decoder can achieve 248 MB/s with an estimated area of 0.31 mm² including the embedded memory to store the received words. Compared with serial decoder, the proposed parallel architecture can achieve 8 times throughput with less than 2 times area.

Key words: parallel BCH decoder, decision tree, parallel computation of syndrome, error locator polynomial