关键词: 时钟偏斜, 时钟偏斜规划, 逻辑综合, 面积优化

Abstract: A new clock skew scheduling algorithm is proposed. This algorithm generates timing constraints which can effectively promote the area optimization of logic synthesis. During clock skew scheduling, the slacks are not equally assigned to the arcs in critical cycles. In stead, they are assigned according to the arc weights which are calculated considering the area impact of the corresponding paths. Experiment results show that this approach can efficiently reduce area of logic synthesis results compared with the traditional clock skew scheduling algorithm, without degrading the performance.

Key words: clock skew, clock skew scheduling, logic synthesis, area optimization