关键词: 泄漏功耗, 流水化指令缓冲存储器, 动态电压调节

Abstract: Pipelined level one instruction cache (PIL1) has been proposed to improve instruction fetch bandwidth in high frequency processor. However, few researches in the literature have focused on reducing the leakage power in PIL1. Here,the authors observe that the PIL1 structure naturally lends itself to provide inherent leakage power saving opportunities. Based on this observation, the authors propose to manage cache line activities according to the demand of the fetch address, which activates only the requested line and keeps others in low-voltage mode, thereby saving leakage power effectively. Simulation results demonstrate that the PIL1 leakage power is reduced by an average of 77.3%. Meanwhile, the performance degradation is only 0.32% and no timing overhead is induced.

Key words: leakage power, pipelined instruction cache, dynamic voltage scaling