北京大学学报（自然科学版）

一种高效并行处理结构的H.264去块滤波器

赵悦汐1,蒋安平   

  1. 北京大学信息技术学院微电子系，北京，100871；1通讯作者，E-mail:zhaoyx@ime.pku.edu.cn
  • 收稿日期:2006-09-01 出版日期:2007-09-20 发布日期:2007-09-20

An Effective Parallel Processing Architecture for Deblocking Filter in H.264

ZHAO Yuexi1JIANG Anping   

  1. SoC Lab, Department of Microelectronics, Peking University, Beijing, 100871； 1Corresponding Author, E-mail: zhaoyx@ime.pku.edu.cn
  • Received:2006-09-01 Online:2007-09-20 Published:2007-09-20

PDF (翻译版)

摘要： 针对H.264视频编码标准中的去块滤波部分提出了一种基于时间的高效并行处理方法。为了降低对存储器的要求，同时提高中间数据的复用效率，采用了一种改进的滤波顺序，使得对外部存储器的读/写操作可以与滤波操作并行执行。另外，由于外部数据的预先载入技术，有效地降低了外部存储器的结构复杂度。与过往技术相比，这种单数据口外部存储结构的去块滤波器单宏块滤波处理周期总数减少了9.6%～74.4%,有效地提高了处理能力。

关键词: H.264, 去块效应滤波, VLSI, 并行处理

Abstract: An efficient parallel processing method for deblocking filter design in H.264 video coding standard is presented. In order to reduce the memory reference and make the intermediate data reused as soon as possible, an advanced filtering order is taken, and so read/write operation on external memory is executed in parallel with filtering computation. Furthermore, preloading operation is used to reduce complexity of memory structure. As a result, the processing cycles of the proposed architecture with single-port memory architecture is reduced by 9.6%-74.4% compared with the advanced architecture of previous proposals.

Key words: H.264, deblocking filter, VLSI, parallel processing

中图分类号: 

版权所有 © 《北京大学学报（自然科学版）》编辑部
技术支持：北京玛格泰克科技发展有限公司