关键词: RSA密码处理器, 蒙哥马利模乘法器, 模乘幂运算器, 公钥基础设施, 超大规模集成电路, 脉动阵列, 深亚微米技术, 中国剩余定理

Abstract: A novel and generic approach is presented to the hardware implementation of the RSA cryptoprocessor in deep submicro (DSM) technology with a redesigned systolic array. With deep submicro technology scaling, integrated circuit performance bottleneck has shifted from logic gates to global interconnection. Besides using the systolic architecture which is popular in hardwarebased RSA systems, a blockbased scheme is proposed to eliminate global signals, with a pipelined bus to convey data globally. The control signals and intermediate results used for sequential multiplications are transmitted by shift registers. All signals, except for the clock signal, are limited in one block or between two adjacent blocks. The Chinese Remainder Theorem (CRT) technique increases the decryption data rate by a factor of four. Two redundant blocks are added to adapt to the online partition of the multiplier and the variation of the length of P and Q in CRT mode. The blockbased global signal transportation scheme and the redundancy scheme are quite different from those of previous works.

Key words: RSA cryptoprocessor, Montgomery modular multiplier, modular exponentiator, public-key infrastructure (PKI), VLSI, systolic array, deep submicro (DSM) technology, Chinese Remainder Theorem (CRT)