Volumetric Display System Based on FPGA and DLP Technologies
CAO Jian1,2, JIAO Hai2, WANG Yuan1, ZHANG Xing1,2
1. Key Laboratory of Microelectronic Devices and Circuits MOE, Institute of Microelectronics, Peking University, Beijing 100871; 2. School of Software and Microelectronics, Peking University, Beijing 102600;
CAO Jian,JIAO Hai,WANG Yuan,ZHANG Xing. Volumetric Display System Based on FPGA and DLP Technologies[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.
HUANG Ying,CUI Xiaoxin,WEI Wei,ZHANG Xiao,LIAO Kai,LIAO Nan,YU Dunshan.
Research on DPA Resistant Circuit for FPGA
[J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2014, 50(4): 652-656.