Acta Scientiarum Naturalium Universitatis Pekinensis

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CMOS Combinational Circuit Leakage Power Reduction Using Genetic Algorit

ZHAO Xiaoying1YI Jiangfang, TONG Dong, CHENG Xu   

  1. Micro Processor Research & Development Center, Peking University, Beijing, 100871; 1Corresponding Author,
  • Received:2006-09-01 Online:2007-05-20 Published:2007-05-20



  1. 北京大学微处理器研究开发中心,北京,100871; 1通讯作者,

Abstract: A leakage power reduction platform for CMOS combinational circuits by means of input vector control is presented. Genetic algorithm is used for searching minimum leakage vector and circuit status difference is used as fitness function. Experimental results show that this circuit status difference based genetic algorithm can achieve satisfied leakage power reduction, and runtime is reasonable. This method has no requirement for HSpice simulation and independent from target technology library.

Key words: CMOS combinational circuit, leakage power reduction, input vector control, genetic algorithm, circuit status difference

摘要: 面向基于标准单元的CMOS组合电路,利用输入向量控制技术,采用遗传算法作为求解手段,建立了CMOS组合电路静态功耗优化环境。在遗传算法中利用电路状态差异度作为适应度函数,求解使电路静态功耗最小的输入向量。实验结果表明,使用该方法能明显优化静态功耗,运行时间合理,不需要进行HSpice模拟,摆脱了对目标工艺的依赖。

关键词: CMOS组合电路, 静态功耗优化, 输入向量控制, 遗传算法, 电路状态差异度

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