Abstract: An efficient low complexity H.264 VBSME (variable-block-size motion estimation) VLSI (very large scale integrated) architecture is designed, in which a MB-size input buffer, 17×16 snake scan register array, 8×8 PE array,4×4 SAD-adder-tree are used and a four-step VBS MV generator structure is proposed to reduce the hardware cost for wireless video communication applications. Compared with the MB-level VBSME structure, the total count of gates is reduced to 37%, the delay of critical path is shorten from 9.8 ns to 8.2 ns, and nearly 50.3% power is saved and the main data-path width is narrowed to 25%, but all MB characters are reserved. Its low-hardware-complexity performance makes it suitable for the integration of H.264 encoder in wireless video communication applications.

Key words: H.264, VBSME, SAD, VLSI, video communication

摘要： 针对无线视频通讯H.264编码器关键技术VBSME VLSI实现，提出了一种低复杂度结构，该结构由宏块输入缓存器，17×16 蛇形扫描寄存器阵列， 8×8 PE阵列，4×4 SAD加法树和四步可变块运动矢量生成器组成。在有效保持所有的H.264宏块特性的基础上，相对于宏块级的VBSME结构，通过采用新提出的四步可变块运动矢量生成器和双时钟频率调谐技术，主要的数据通道宽度缩减到25%, 硬件代价缩减到37％，关键路径延时由9.8?ns减少到8.2?ns,功耗约降低了50.3％。

关键词: H.264, VBSME, SAD, VLSI, 视频通讯