Acta Scientiarum Naturalium Universitatis Pekinensis

Previous Articles     Next Articles

Realization of 6, Tap Finite Impulse Response Interpolation Filter for H.264/AVC Encoder

WANG Qingchun1, CAO Xixin2, LU Weijun2, HE Xiaoyan3CAO Jian2   

  1. 1Key Laboratory of Integrated Microsystems,Shenzhen Graduate School, Peking University, Shenzhen, 518055;Corresponding Author,; 2School of Software and Microelectronics, Peking University, Beijing, 102600;3Department of Physics and Computer Science, Ankang College, Ankang, 725000
  • Received:2006-06-29 Online:2007-05-20 Published:2007-05-20



  1. 1北京大学深圳研究生院集成微系统重点实验室,深圳,518055;通讯作者,; 2北京大学软件与微电子学院,北京,102600;3安康学院物理与计算机系,安康,725000

Abstract: It is proposed that four hardware architectures of 6, tap finite impulse response interpolation filter for the design of H.264/AVC encoder (SOC). Moreover, based on comparative analysis of Synopsys Design Compiler to implement the hardware at the same constraint, an efficient half pixel interpolation filter (6, tap FIR) architecture had been given finally.

Key words: H.264/AVC video encoder, tap finite impulse response interpolation filter, chip area, delay

摘要: 针对H.264/AVC视频编码器的系统芯片设计,提出了6阶1/2像素插值滤波器的4种具体实现结构;并且在相同的约束条件下,使用Synopsys综合工具比较了各自的实现代价,最终给出了6阶1/2像素插值滤波器的优化实现结构。

关键词: H.264/AVC视频编码器, 6阶插值滤波器, 芯片面积, 路径延迟

CLC Number: