Acta Scientiarum Naturalium Universitatis Pekinensis

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A High Resolution Low Power Sample and Hold Module Dedicated to a Pipelined ADC

JIN Rui, ZHANG Tianyi, YANG Xin   

  1. Shenzhen Graduate School, Peking University, Shenzhen, 518055; Department of Microelectronics, Peking University, Beijing, 100871
  • Received:2005-12-22 Online:2006-09-20 Published:2006-09-20



  1. 北京大学深圳研究生院,深圳,518055; 北京大学微电子系,北京,100871

Abstract: A high performance sample-and-hold(S/H) circuit dedicated to a high resolution analog to digital converter is designed and implemented in 0.25μm CMOS process. The sampling rate of this proposed S/H module is 20MHz with a bandwidth of 10MHz, the full scale of the sampled fully differential signal is 2V with the 2.5V power supply. Instead of the traditional charge transfer architecture, a fully differential flip-around architecture is used to reduce the power consumption. In order to improve the signal to noise ratio(SNR), a bootstrapped switch is implemented in two places. Hspice simulation shows that it achieves a SFDR of 92.4dB for 5MHz input signal. This circuit is integrated to one 14bit 20MHz pipelined ADC.

Key words: sample and hold, ADC, bootstrapped switch, gain-boosted amplifier

摘要: 介绍了一个用于高精度模数转换器,采用 0.25μm CMOS工艺的高性能采样保持电路。该采样保持电路的采样频率为 20MHz,允许最大采样信号频率为 10MHz,在电源电压为 2.5V 的情况下,采样信号全差分幅度为 2V。通过采用全差分flip-around结构,而非传统的电荷传输构架,因而在同等精度下,大大降低了功耗。为了提高信噪比,采用自举开关。Hspice仿真结构显示:在输入信号为 5MHz 的情况下,无杂散动态范围(SFDR)为 92.4dB. 该电路将被用于一个14位 20MHz 流水线模数转换器。

关键词: 采样保持, 模数转换器, 自举开关, 增益增强放大器

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