Acta Scientiarum Naturalium Universitatis Pekinensis

Previous Articles     Next Articles

A Novel Latched Comparator with Low Kickback Noise

ZHANG Xin1, YU Dunshan, SHENG Shimin   

  1. Institute of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing,100871; 1E-mail:
  • Received:2005-12-09 Online:2006-09-20 Published:2006-09-20



  1. 北京大学信息科学技术学院微电子研究所,北京,100871;1E-mail:

Abstract: A new latched comparator architecture was proposed. Because of its very low kickback noise feature, it is especially suitable for differential analog-to-digital converters (ADCs). Simulated results of the proposed circuit in a 0.35μm standard CMOS technology show that this comparator achieves a sampling speed of 400 Ms/s at 3.3V supply, with a kickback noise 88% lower than conventional schemes.

Key words: analog-to-digital(A/D) conversion, parallel ADC, high-speed comparators, kickback noise

摘要: 提出了一种新的闩锁型比较器结构。由于它的低kickback噪声特性,此比较器特别适合应用于差分模拟-数字转换器(ADCs)。电路采用标准 0.35μm 的工艺进行模拟,结果显示此比较器在 3.3V 电源下采样频率为 400Ms/s,并且kickback噪声比传统结构减少了88%。

关键词: 模拟-数字转换, 平行ADC, 高速比较器, kickback噪声

CLC Number: