Acta Scientiarum Naturalium Universitatis Pekinensis

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Analysis and Design of Low Power XOR-XNOR Circuits

LAN Jinghong, WANG Fang, JI Lijiu, JIA Song   

  1. Department of Microelectronics, Peking University, Beijing, 100871
  • Received:2005-06-27 Online:2006-05-20 Published:2006-05-20



  1. 北京大学微电子系,北京,100871

Abstract: Two novel low power pass transistor based XOR-XNOR circuits are proposed, UPPL (Unsymmetrical Push Pull Pass Transistor Logic) and CPPL (Complementary Push Pull Pass Transistor Logic). They both input single rail signals and output dual rail signals, which can get XOR and XNOR signals simultaneously. The output signals are full swing voltage. Hspice simulation under 0.18μm technology 1.8V voltage showed improvement on speed and power-delay product compared with some other circuits. Compared with the latest circuits, which was proposed by Mohamed Elgamel in 2003, the UPPL and CPPL circuits have 61.0% and 58.4% decreases on power delay product respectively without load. And with fanout three, they have 25.3% and 45.3% decreases respectively.

Key words: low power, Boolean logic, XOR circuit, XOR-XNOR logic, pass transistor logic

摘要: 提出了2种传输管实现的新型低功耗异或门结构,UPPL(Unsymmetrical Push Pull Pass Transistor Logic)结构和CPPL(Complementary Push Pull Pass Transistor Logic)结构,两者均为非互补输入,互补输出,都能够同时产生异或和同或信号,且输出为全摆幅电压。对新结构在0.18μm工艺1.8V电压下进行了hspice仿真,与已有同类电路在速度、功耗和功耗延迟乘积方面进行了比较。UPPL结构和CPPL结构与2003年Mohamed Elgamel提出的最新设计相比,空负载时,功耗延迟乘积项分别有61.0%和58.4%的降低;扇出为3时,分别有25.3%和45.3%的降低。

关键词: 低功耗, 布尔逻辑, 异或门, 异或同或逻辑, 传输门实现

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