Design of a High Speed Low Power Time-to-Digital Converter Based on Multi-stage Amplification Structure

doi:10.13209/j.0479-8023.2017.145

Acta Scientiarum Naturalium Universitatis Pekinensis ›› 2018, Vol. 54 ›› Issue (2): 299-306.DOI: 10.13209/j.0479-8023.2017.145

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Design of a High Speed Low Power Time-to-Digital Converter Based on Multi-stage Amplification Structure

FAN Chuanqi¹, JIA Song^2,†, WANG Zhenyu¹, YAN Wei¹, WU Zebo¹

1. School of Software and Microelectronics, Peking University, Beijing 100871
2. Key Laboratory of Microelectronics Devices and Circuits (MOE), School of Electronics Engineering and Computer Science, Peking University, Beijing 100871

Received:2016-12-16 Revised:2017-03-13 Online:2018-03-20 Published:2018-03-20
Contact: JIA Song, E-mail: jias(at)pku.edu.cn

基于多级放大结构的高速低功耗时间数字转换器设计

范传奇¹, 贾嵩^2,†, 王振宇¹, 严伟¹, 吴泽波¹

1. 北京大学软件与微电子学院, 北京 100871
2. 教育部微电子器件和电路重点实验室, 北京大学信息科学技术学院, 北京 100871

通讯作者: 贾嵩, E-mail: jias(at)pku.edu.cn

Abstract

Abstract:

The authors present a time-to-digital converter based on multi-stage amplification structure. This structure consists of coarse stage and fine stage. Coarse stage utilizes delay line to get the residue which is less than a buffer’s delay. A small area and low power residue selecting logic is designed. In the fine stage, 2× time amplifier and half judger is utilized to generate 4 binary codes from MSB to LSB. Simulation in SMIC 65 nm process shows that the new structure has a high conversion speed up to 470 MS/s and power consumption is 1.3 mW at 100 MHz with the resolution of 1.44 ps and range of 736 ps. An accurate gain robust to PVT variation can be achieved with the calibration of the time amplifier, so a good integral nonlinearity is obtained.

Key words: time-to-digital converter, time amplifier, high speed, low power

摘要：

提出一种多级放大时间数字转换器新型结构。该结构由粗测和细测组成, 粗测部分利用延时链得到小于一个延时单元的关键余量, 并设计了面积小、功耗低的关键余量选择逻辑。细测部分, 利用两倍时间放大器和过半判断器从高位到低位依次产生4位二进制码。在SMIC 65 nm工艺下仿真, 新型结构的分辨率为1.44 ps, 量程为736 ps, 转换速度可达470 MS/s, 在100 MHz频率下, 平均功耗仅为1.3 mW。对两倍时间放大器设计了校准电路, 提高了抵抗PVT的能力, 得到良好的积分非线性。

关键词: 时间数字转换器, 时间放大器, 高速, 低功耗

CLC Number:

TN453

FAN Chuanqi, JIA Song, WANG Zhenyu, YAN Wei, WU Zebo. Design of a High Speed Low Power Time-to-Digital Converter Based on Multi-stage Amplification Structure[J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2018, 54(2): 299-306.

范传奇, 贾嵩, 王振宇, 严伟, 吴泽波. 基于多级放大结构的高速低功耗时间数字转换器设计[J]. 北京大学学报（自然科学版）, 2018, 54(2): 299-306.

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Design of a High Speed Low Power Time-to-Digital Converter Based on Multi-stage Amplification Structure

基于多级放大结构的高速低功耗时间数字转换器设计

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