Acta Scientiarum Naturalium Universitatis Pekinensis

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A Multi-Layer Charge-Pump Phase-Locked Loop Behavioral Model

FENG Wennan, LIU Ling, CHEN Zhongjian, JI Lijiu   

  1. Department of Microelectronics, Peking University, Beijing, 100871; E-mail:
  • Received:2003-11-04 Online:2004-05-20 Published:2004-05-20


冯文楠, 刘凌, 陈中建, 吉利久   

  1. 北京大学微电子学系, 北京, 100871; E-mail:

Abstract: A novel multi-layer Charge-Pump Phase-Locked Loop (CP-PLL) behavioral model is presented in this paper. In contrast to conventional CP-PLL models, the multi-layer model offers great flexibility of trading off the speed and accuracy of simulation by describing the ideal and nonideal characteristics in separated layers that can be configured individually. Also with a specific layer the approach provides the ability of carrying out noise simulation in time domain. The multi-layer model is built in Verilog-A and simulated by SpectreTM. A simulation speed up factor of 20 to 99 is achieved with reasonable loss of accuracy.

Key words: mixed-signal system, behavioral modeling, behavioral simulation, phase-locked-loop

摘要: 提出了一种全新的电荷泵锁相环的行为级建模方法。采用多层模型,能根据需要在仿真的精度和速度间进行权衡,在可独立配置的不同层次中描述锁相环系统的理想行为和非理想行为。与传统的电荷泵锁相环模型相比,灵活性大大提高。该建模方法还提供了一个专用层进行时域噪声仿真,使得系统的噪声特性得以更准确的验证。该多层模型用Verilog-A建立,用SpectreTM进行仿真。在精度损失很小的情况下仿真速度有20到99倍的提高。

关键词: 混合信号系统, 行为级建模, 行为级仿真, 锁相环

CLC Number: