Abstract: A novel double-readout trace-back(DRTB) algorithm that used in Viterbi Decoderfor likelihood path series searching is developed by analyzing the rule of trace-back operation. It increases the throughput rate up to 4 times without any additonal hardware overhead. The structural ASIC design of surviving path memory unit (SMU) toward DRTB algorithm is described and it is applied in a Viterbi Decoder IC design. With being fabricated, the test results indicate that the DRTB algorithm and circuit design are successful as prediction.

Key words: viterbi decoder, trace-back, double-readout algorithm

摘要： 在分析维特比译码器回溯算法的基础上，归纳出回溯算法的规律，提出了双读出回溯(DRTB)算法。计算表明，DRTB算法在不增加硬件开销的情况下，使回溯运算速度达到原来的4倍。本文还介绍了基于DRTB算法幸存路径存储器单元(SMU)的ASIC结构和物理设计。对半导体集成电路的测试表明，本文提出的DRTB算法及电路结构是成功的。

关键词: 维特比译码器, 回溯, 双读出算法