Acta Scientiarum Naturalium Universitatis Pekinensis

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Design of AES Coprocessor Used on the Node of Wireless Sensor Network

LI Yuwen1, ZHANG Xing1, JIANG Anping2   

  1. 1. Department of Microelectronic, Peking University, Beijing 100871; 2. Beijing Micro-Electronics Institute, Beijing 100076;
  • Received:2008-05-19 Online:2009-05-20 Published:2009-05-20



  1. 1.北京大学微电子学系,北京100871;2.北京微电子技术研究所,北京100076;

Abstract: To design an AES coprocessor used on the mode of WSN(wireless sensor network), a method of reusing some given modules or other resources is presented. Also, a novel circuit of mixcolumn module is designed to reduce the whole area of the system. Some methods such as insulation of the operands, dynamic power management and optimization of coding are adopted to reduce the power consumption. The AES coprocessor on the node of WSN of this paper is integrated in Virtex4 FPGA, and meets all the requirements of WSN.

Key words: AES, low power, low cost, FPGA, MixColumn

摘要: 针对无线传感器网络的特点,采用加解密复用,子模块复用技术,低成本MixColumn模块的设计,以及操作数隔离,编码优化,动态功耗管理等方法,基于Xilinx公司的Virtex4系列FPGA,完成了用于无线传感器网络节点中的AES-128加解密算法协处理器的优化设计以及FPGA实现。该设计处理速度、面积功耗等都满足常用无线传感器网络节点的要求。

关键词: AES, 低功耗, 低成本, FPGA, 列混合

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