Abstract: The decoding algorithm is investigated and an improved architecture for the decoders is presented. The architecture makes variable nodes and check nodes work for two different code words at the same time. And the architecture is not only fit for full-parallel LDPC decoders but also fit for the semi-parallel decoders which are mostly used in the practical communication systems. Asemi-parallel LDPC decoder with code length equal to 1008bits is implemented based on this architecture on FPGA platform. Synthesize results show that the improved architecture can improve the efficiency of the logic cells. And the throughputs of information bits attain 45 Mbps which is twice of the throughputs of the decoder without the improved architecture.

Key words: low density parity check (LDPC) codes, decoder, FPGA, high throughput

摘要： 通过对LDPC码(低密度奇偶校验码)的迭代译码算法的分析，提出了一种同时能够对两个码字进行译码，使得译码器中的变量节点和校验节点交替被两个码字使用的译码器结构。该结构不仅适用于全并行结构的LDPC码译码器，也适用于目前广泛采用的半并行结构译码器。以此结构为基础，实现了一个长度为1008bit，改进半并行结构的LDPC码译码器。此结构能够充分利用现有半并行结构译码器的逻辑资源，将译码器数据吞吐率提高近一倍。测试结果表明，该译码器的有效信息速率达到45Mbps。

关键词: 低密度奇偶校验码（LDPC码）, 译码器, FPGA, 高速实现