An Improvement in the VLSI Implementation of Montgomery Algorithm

Acta Scientiarum Naturalium Universitatis Pekinensis

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An Improvement in the VLSI Implementation of Montgomery Algorithm

ZHANG Yihao, TIAN Ze, YU Dunshan, SHENG Shimin

Department of Microelectronics, Peking University, Beijing, 100871

Received:2002-12-16 Online:2004-01-20 Published:2004-01-20

一种Montgomery模乘算法硬件实现的改进电路

张怡浩,田则,于敦山,盛世敏

北京大学微电子学系，北京，100871

Abstract

Abstract: Modular exponentiation of large operands is the kernel operation in many public-key cryptosystems, RSA algorithm for instance. Montgomery algorithm is often used as a solution. In the VLSI implementation of Montgomery algorithm, the speed is the top target. An improvement is proposed with little or even no increase in the hardware area but apparently saving much time.

Key words: Montgomery, RSA, VLSI Implementation

摘要： 速度与面积是数字集成电路设计的两个重要目标，由于它们之间通常是一种相互制约的关系，所以往往要在一定程度上进行折中。作者提出的改进方法可以在几乎不增加硬件面积的条件下有效地提高速度。

关键词: Montgomery, RSA, VLSI硬件实现

CLC Number:

ZHANG Yihao,TIAN Ze,YU Dunshan,SHENG Shimin. An Improvement in the VLSI Implementation of Montgomery Algorithm[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.

张怡浩,田则,于敦山,盛世敏. 一种Montgomery模乘算法硬件实现的改进电路[J]. 北京大学学报（自然科学版）.

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URL: https://xbna.pku.edu.cn/EN/

https://xbna.pku.edu.cn/EN/Y2004/V40/I1/80

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An Improvement in the VLSI Implementation of Montgomery Algorithm

一种Montgomery模乘算法硬件实现的改进电路

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