An Analytical Model of Gate-All-Around Nanowire Tunnel FET

Acta Scientiarum Naturalium Universitatis Pekinensis

An Analytical Model of Gate-All-Around Nanowire Tunnel FET

HE Yuan^1,2, WANG Juncheng², WEI Kangliang², LIU Xiaoyan²

1. Shenzhen Graduate School, Peking University, Shenzhen 518055; 2. Institute of Microelectronics, Peking University, School of Electronics Engineering and Computer Science, Beijing 100871;

Received:2013-03-28 Online:2014-07-20 Published:2014-07-20

基于环栅纳米线隧穿场效应晶体管的解析模型

何媛^1,2,王骏成²,魏康亮²,刘晓彦²

1. 北京大学深圳研究生院, 深圳 518055; 2. 北京大学信息科学技术学院微电子学研究院, 北京 100871;

Abstract

Abstract: An analytical model for gate-all-around (GAA) nanowire tunnel FETs (TFET) is proposed. It proves that the TFETs have good performance in sub-threshold region. Research shows that the sub-threshold slop of GAA nanowire TFET is proportional to several model parameters, such as the diameter, the thickness of oxide layer, and the voltage of drain. The model and simulation would lay a good foundation for its future application in low-power circuits.

Key words: tunnel FETs, analytical model, low power, sub-threshold slop

摘要： 对环栅纳米线结构的隧穿场效应晶体管进行建模分析, 给出电流解析模型, 证明隧穿场效应管有良好的亚阈特性。研究发现, 环栅纳米线隧穿场效应管的亚阈值斜率SS的大小与圆柱体硅直径d_nw、环栅氧化层厚度t_ox以及漏电压V_dd的变化规律均成正比, 即圆柱体硅直径d_nw、环栅氧化层厚度t_ox和漏电压V_dd越小, 亚阈区的性能越好。这一模型的研究为场效应晶体管在低功耗电路中的应用打下良好基础。

关键词: 隧穿晶体管, 解析模型, 低功耗, 亚阈值斜率

CLC Number:

TN386

HE Yuan,WANG Juncheng,WEI Kangliang,LIU Xiaoyan. An Analytical Model of Gate-All-Around Nanowire Tunnel FET[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.

何媛,王骏成,魏康亮,刘晓彦. 基于环栅纳米线隧穿场效应晶体管的解析模型[J]. 北京大学学报（自然科学版）.

[1]	FAN Chuanqi, JIA Song, WANG Zhenyu, YAN Wei, WU Zebo. Design of a High Speed Low Power Time-to-Digital Converter Based on Multi-stage Amplification Structure [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2018, 54(2): 299-306.
[2]	QIAN Zebin, YAN Wei. Low Resource Consumption Design of Digital Decimation Filter [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2018, 54(2): 315-319.
[3]	TANG Wenyi,JIA Song,XU Heqing,MENG Qinglong,WANG Yuan,ZHANG Ganggang. A New High Speed Current Mode Sense Amplifier for Low Power SRAM [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2014, 50(4): 681-684.
[4]	HU Ziyi,ZHOU Yinhao,CHEN Lan,ZHANG Xu,WANG Teng,XIE Zheng. Low Power Integrated Circuit Technologies in Wireless Sensor Networks [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2014, 50(4): 664-674.
[5]	LIAO Kai,CUI Xiaoxin,LIAO Nan,WANG Tian,ZHANG Xiao,HUANG Ying,YU Dunshan. Efficient Implementation of Generalized Binary Hessian Curve Based Processor for RFID [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2014, 50(4): 657-663.
[6]	HOU Zhongyuan,LIU Junhua,LIAO Huailin,ZHANG Xing. A Low-Power AGC for BD-II/GPS Receiver [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2014, 50(4): 627-631.
[7]	FENG Xiaoxing,WANG Xin’an,ZHANG Xing,GE Binjie. A Passive UHF RFID Transponder with Novel Clock Generator [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2011, 47(3): 404-410.
[8]	LI Yuwen,ZHANG Xing,JIANG Anping. Design of AES Coprocessor Used on the Node of Wireless Sensor Network [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2009, 45(3): 426-430.
[9]	ZHANG Shiqun,YU Dunshan,SHENG Shimin. A Low Power Pipeline FFT Processor Based on Data Statistical Characteristics [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2008, 44(1): 31-36.
[10]	DUAN Lian,XU Hu,WANG Kui,CHENG Xu. Power-Aware Gated Clock Routing with Merging Cost Backward Annotation Using Simulated Annealing Method [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2007, 43(5): 694-702.
[11]	LIU Dan,LU WengaoCHEN Zhongjian,JI Lijiu,ZHAO Baoying. Novel Low Power QSBDI Structure for IR ROIC [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2007, 43(5): 659-663.
[12]	LIU Dan,LU Wengao,CHEN Zhongjian,JI Lijiu,ZHAO Baoying. Novel Low Power Column Stage Design of 302×288 Infrared ROIC [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2007, 43(1): 67-71.
[13]	LAN Jinghong,WANG Fang,JI Lijiu,JIA Song. Analysis and Design of Low Power XOR-XNOR Circuits [J]. Acta Scientiarum Naturalium Universitatis Pekinensis, 2006, 42(3): 380-384.