Abstract: The authors analyze the detailed process of calculator schedule in high speed FIR (finite impose response) digital filter with add-and-shift algorithm based on FPGA (field programmable gate array). Different calculation situations and related schedule schemes are discussed and a clear rule of optimization is proposed. At last, an example of a 16-order FIR filter is implemented on Xilinx Spartan 3 3s1000ft256 FPGA platform. The occupied resource is 11.7% less than the one generated without optimization and/or 29.7% less than the one generated by Xinlinx Coregen^TM with distribute arithmetic (DA), respectively.

Key words: FIR filter, add-and-shift, calculator schedule, FPGA

摘要： 针对原有在FPGA上实现高速FIR滤波器的移位加算法，进一步分析了算子调度的具体过程，讨论了在不同情况下该算法所能达到的最省资源的算子调度方案，并提出了优化的具体规则。在Xilinx spartan3系列FPGA上的实现结果表明，对于16阶固定系数FIR滤波器，相比于原有的移位加算法以及Xilinx Coregen^TM生成的同等规模的分布式算法滤波器，采用优化算法后的FIR滤波器可节省资源分别达11.7%和29.7%。

关键词: FIR滤波器, 移位加, 算子调度, FPGA