A High Efficient Method to Generate the Verification Vector of ICs

Abstract

Abstract: Verification is very important in designing digital systems. It has become a bottleneck in the modern digital system design cycle. In an effort to improve current verification method based on simulation, this paper presents a method for the generation of simulation vectors using FSM. It can improve the coverage of the state space.

Key words: specification, fsm, coverage, event, verification vectors

摘要： 设计验证（Design Verification）在数字系统设计中已经非常重要。功能验证成为了现代数字系统设计周期地瓶颈。作为对基于仿真地验证方法改进的一次尝试，介绍了一种基于有限状态机生成测试向量的方法。它有效地提高了状态空间的覆盖率。

关键词: 设计规范, 有限状态机, 覆盖率, 事件, 验证向量

CLC Number:

SUN Zhao,WANG Yong. A High Efficient Method to Generate the Verification Vector of ICs[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.

孙钊,王勇. 芯片功能验证流的高效生成方法[J]. 北京大学学报（自然科学版）.

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URL: https://xbna.pku.edu.cn/EN/

https://xbna.pku.edu.cn/EN/Y2007/V43/I1/92

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A High Efficient Method to Generate the Verification Vector of ICs

芯片功能验证流的高效生成方法

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