Acta Scientiarum Naturalium Universitatis Pekinensis ›› 2022, Vol. 58 ›› Issue (6): 1015-1022.DOI: 10.13209/j.0479-8023.2022.096

Previous Articles     Next Articles

A Hardware Accelerator for SSD Object Detection Algorithm Based on FPGA

XIE Hao1, CAO Jian1,†, LI Pu1, ZHAO Xiongbo2, ZHANG Xing1,†   

  1. 1. School of Software & Microelectronics, Peking University, Beijing 102600 2. Beijing Aerospace Automatic Control Institute, Beijing 100854
  • Received:2022-01-13 Revised:2022-06-07 Online:2022-11-20 Published:2022-11-20
  • Contact: CAO Jian, E-mail: caojian(at), ZHANG Xing, E-mail: zhx(at)


谢豪1, 曹健1,†, 李普1, 赵雄波2, 张兴1,†   

  1. 1. 北京大学软件与微电子学院, 北京 102600 2. 北京航天自动控制研究所, 北京 100854
  • 通讯作者: 曹健, E-mail: caojian(at), 张兴, E-mail: zhx(at)
  • 基金资助:


A hardware accelerator of object detection algorithm based on FPGA is designed to accelerate the computation of SSD object detection algorithm. Loop tiling and loop unrolling are used to optimize the loops of convolution and pooling, and can be re-configurated in any parallelism. In order to reduce data transmission time, feature maps are reorganized based on AXI, without any hardware resource overhead. After implementing the hardware accelerator to Xilinx ZCU development board, it can accelerate SSD at a performance of 534.72 GOPS, and the inference time is 113.81 ms.

Key words: convolutional neural network, object detection, hardware acceleration, field programmable gate array (FPGA), ARM


设计了一种基于FPGA的目标检测算法的硬件加速器, 采用循环分块和循环展开的方式来优化卷积池化循环, 可以以任意并行度进行卷积和池化计算。使用一种基于AXI总线的数据重排序方式, 在不带来额外硬件资源开销的情况下, 对特征图进行重排序, 可以降低数据传输时间。将该硬件加速器部署至Xilinx ZCU 102开发板进行验证, 结果表明SSD算法前向推理性能为534.72 GOPS, 推理时间为113.81 ms。

关键词: 卷积神经网络, 目标检测, 硬件加速, 现场可编程门阵列, ARM