Abstract: A low latency endpoint implementation scheme compliant with specification V1.3 is described. A novel architecture is proposed where most modules in transmitting and receiving paths are designed to work in cut-through modes with the purpose of generating short and fixed latencies. To the transaction interface, requests and responses can be issued from different user-defined ports and sent through the proposed sharable transfer paths. Concurrent transactions can be kept in order by safety arbitration mechanisms. Furthermore, abandoned packets can be cancelled by the enhanced four-queue buffers to prevent invalid transmissions. To the 1x/4x serial physical interfaces, reliable transmissions of packets and control symbols are achieved. Crucial link managements including flow control, error detection and recovery are also supported. Compared with the reference designs, the proposed scheme can achieve lower latency and higher throughput performances. Furthermore, the feasibility and effectiveness have been confirmed by FPGA verifications. Therefore, this scheme is considered applicable in the next-generation high speed embedded interconnections.

Key words: RapidIO, SRIO endpoint, embedded interconnection, serial physical layer, low latency

摘要： 提出一种可兼容V1.3版本规范的低时延端点实现方案。 在该方案中, 输出和输入路径上的多数模块工作在直通模式以产生稳定的低时延。对于事务接口, 请求和响应可以通过不同的用户定义端口输入并共享传输路径, 而且同时发起的事务能在安全的仲裁机制下保持有序传送。为了防止无效的数据传输, 废弃的事务包将会被改进的4队列式缓冲模块撤销。对于串行物理接口, 1x/4x链路能为事务包和控制符号提供可靠的数据传送, 并实现流量控制、错误检测及恢复等关键的链路管理功能。与参考设计相比, 此方案能获得更低的传输时延和更高的数据吞吐率。此方案的功能和性能已通过FPGA平台的验证, 因此能满足下一代高速嵌入式互连的应用需求。

关键词: RapidIO, SRIO端点, 嵌入式互连, 串行物理层, 低时延