Acta Scientiarum Naturalium Universitatis Pekinensis

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Design of Reconfigurable Processor ReMAP for Video Codec

DAI Peng, YONG Shanshan, WANG Xin’an, ZHANG Xing   

  1. Key Lab of Integrated Microsystem Science Engineering and Application, Shenzhen Graduate School, Peking University,Shenzhen 518055;
  • Received:2010-03-27 Online:2011-05-20 Published:2011-05-20


戴鹏, 雍珊珊, 王新安, 张兴   

  1. 北京大学深圳研究生院集成微系统科学工程与应用重点实验室, 深圳518055;

Abstract: A coarse-grain reconfigurable processor ReMAP-2 is proposed for video codec applications which shares several important characteristics: compute intensity, parallelism, and locality. ReMAP-2 comprises of a reconfigurable array of processing elements and interconnect network with neighborly connect and segment buses, which possesses good scalability. The architecture can change the function of processing elements and the data path of the reconfigurable array by uploading different configuration stream for different applications, which is suit for multiple standard of video codec. The simulation result shows that ReMAP-2 can achieve much better performance than common media processors. The compute capability is close to or same as ASIC implementation and meanwhile it has upstanding flexibility.

Key words: reconfigurable processor, H.264, codec, DCT, dynamic reconfiguration

摘要: 针对当前视频高清编解码的计算密集性、并行性和数据局部性的特点, 提出一个粗粒度的可重构处理器ReMAP-2。该处理器由一个可重构的计算单元阵列构成,通过由临近直联和分段式总线组成的互联网络完成数据通信任务, 具有良好的扩展性。计算阵列针对不同应用,通过加载不同配置信息流实时改变运算单元的计算功能和连接方式,支持多种格式的视频编解码应用。仿真验证表明, 可重构处理器 ReMAP-2 在视频编解码应用时较常用的媒体处理器具有较大幅度的性能加速, 处理性能达到或接近于ASIC水平,同时具有较高的应用灵活性。

关键词: 可重构处理器, H.264, 编解码, DCT, 动态重构

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