Abstract: A hierarchically modularized design based clock accurate simulator platform ReSim is proposed for the flexible interconnection, expandability and dense computational characteristics of reconfigurable processor ReMAP. The simulator is designed under three hierarchy software framework, which contains interconnect modules to accelerate various interconnection architecture evaluation, control modules to simulate different compute model. The simulator can quickly establish the reconfigurable processor model and test the function validity of processor architecture, as well as evaluating the performance under the control of clock driving module for the whole system. The result shows that ReSim can support the evaluation and simulation of the reconfigurable processor architecture ReMAP-2 effectively.

Key words: simulator, clock accurate, reconfigurable processor, instruction set, computation model

摘要： 针对可重构处理器 ReMAP( reconfigurable multimedia array processor) 面向视频高清编解码提出的灵活互联、计算资源密集、易于扩展的结构优化需求, 提出了一个基于模块化分层设计、时钟周期精确的可重构处理器仿真平台ReSim。该仿真器基于3 级软件框架层次搭建, 设计了可快速仿真多种互联结构的互联模块、多种计算模型的控制模块等模块化功能单元, 结合时钟驱动模块对全局系统结构的运行驱动, 可快速搭建可重构处理器的目标仿真模型, 验证其正确性和有效性, 精确评估计算性能, 具有可视化、易于调试的特点。经实际测试表明, ReSim 对可重构处理器 ReMAP-2 架构的系统评估与验证予以良好的支持。

关键词: 仿真器, 时钟精确, 可重构处理器, 指令集, 计算模型