Acta Scientiarum Naturalium Universitatis Pekinensis

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A 0.0068mm2 Self-calibration Circuit for Phase Locked Loop

ZHENG Jiapeng1, LI Wei2, YANG Yi2, MA Juncheng2, CHENG Yuhua1, WANG Yangyuan1   

  1. 1. Instisute of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing 100871; 2. Semiconductor Manufacturing International Corporation SMIC, Shanghai 201203;
  • Received:2009-12-08 Online:2011-01-20 Published:2011-01-20



  1. 1. 北京大学信息科学技术学院微电子学研究院, 北京100871; 2. 中芯国际, 上海 201203;

Abstract: A phase locked loop (PLL) using a free-running self-calibration technique is reported. The proposed self-calibration operation is performed during the process of the normal PLL lock period without requiring a voltage-reference block. The new scheme benefits reducing chip area. The area interrelated to calibration circuits is only 0. 0068mm2. The PLL is designed and implemented using SMIC 0.13 μm complementary metal oxide semiconductor (CMOS) process and the measured PLL lock-in frequency range is 25-700 MHz. The phase noise of the output clock at 87. 5 MHz is - 131 dBc/Hz at 1 MHz offset, while the voltage-controlled-oscillator (VCO) is at 700 MHz.

Key words: PLL, self-calibrations, ring oscillator

摘要: 提出了一种可供 CMOS锁相环使用的自由调整的自校准技术。与传统的自校准技术相比, 新的自校准方案不需要使用参考电压源, 而且自校准过程内嵌在锁相环的锁定过程中,所以新的自校准方案减少了芯片的面积:与自校准有关电路的面积只有0.0068mm2。所设计的PLL采用0.13 μm CMOS 工艺, 工作频率范围在 25 ~700MHz 之间。测试表明, 当压控振荡器工作在 700 MHz 的时候, 其 8 倍降频之后的87. 5 MHz 输出信号的相位噪音在1 MHz 频率偏移处为-131 dBc/ Hz。

关键词: 锁相环, 自校准, 振荡环

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