Abstract: A phase locked loop (PLL) using a free-running self-calibration technique is reported. The proposed self-calibration operation is performed during the process of the normal PLL lock period without requiring a voltage-reference block. The new scheme benefits reducing chip area. The area interrelated to calibration circuits is only 0. 0068mm². The PLL is designed and implemented using SMIC 0.13 μm complementary metal oxide semiconductor (CMOS) process and the measured PLL lock-in frequency range is 25-700 MHz. The phase noise of the output clock at 87. 5 MHz is - 131 dBc/Hz at 1 MHz offset, while the voltage-controlled-oscillator (VCO) is at 700 MHz.

Key words: PLL, self-calibrations, ring oscillator

摘要： 提出了一种可供 CMOS锁相环使用的自由调整的自校准技术。与传统的自校准技术相比, 新的自校准方案不需要使用参考电压源, 而且自校准过程内嵌在锁相环的锁定过程中,所以新的自校准方案减少了芯片的面积:与自校准有关电路的面积只有0.0068mm²。所设计的PLL采用0.13 μm CMOS 工艺, 工作频率范围在 25 ～700MHz 之间。测试表明, 当压控振荡器工作在 700 MHz 的时候, 其 8 倍降频之后的87. 5 MHz 输出信号的相位噪音在1 MHz 频率偏移处为-131 dBc/ Hz。

关键词: 锁相环, 自校准, 振荡环