Acta Scientiarum Naturalium Universitatis Pekinensis

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An Improved CMOS PLL with Dual Control Paths

SONG Ying, WANG Yuan, JIA Song, LIU Zhi, ZHAO Baoying   

  1. Key Laboratory of Microelectronic Devices and Circuits, Ministry of Education , Institute of Microelectronics, Peking University, Beijing 100871; , E-mail:
  • Received:2008-08-19 Online:2009-07-20 Published:2009-07-20



  1. 北京大学微电子所,微电子器件与电路教育部重点实验室,北京100871;,

Abstract: The authors propose an improved phased locked loop(PLL) architecture with dual control paths. The two control paths have different voltage controlled oscillat or (VCO) gain. The coarse tuning path has a large VCO gain, and is used to cover operating frequency range. Having a small VCO gain, the fine tuning path determines the loop bandwidth and optimizes the jitter performance. This circuit is fabricated in a 0. 18 μm CMOS logic process. The presented PLL has an output range from 600MHz to 1.6 GHz, and exhibits good jitter characteristic.

Key words: PLL, dual control path, lowjitter

摘要: 提出一种改进的双控制通路锁相环结构。改进锁相环的两个控制通路有不同的压控振荡器增益。其中, 粗调节通路的压控振荡器增益较大, 用来调节锁相环的输 出频率范围; 细调节通路的压控振荡器增益较小, 用来决定环路带宽, 同时优化锁相环的抖动特性。电路芯片采用SMIC 0. 18 μm CMOS Logic 工艺加工。后仿真结果表明该锁相环的输出频率范围为600 MHz到1. 6GHz, 并有良好的抖动特性。

关键词: 锁相环, 双控制通路, 低抖动

CLC Number: