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High-Speed Parallel BCH Decoder Circuit in VLSI

JIN Jie, YU Dunshan   

  1. Department of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing 100871;
  • Received:2008-04-02 Online:2009-03-20 Published:2009-03-20



  1. 北京大学信息科学技术学院微电子系,北京100871;

Abstract: A high speed VLSI decoder architecture is proposed for a standard forward error correction(FEC) in optical network. In the proposed parallel decoder architecture, a novel parallel computation of syndrome is presented to reduce the hardware complexity. A method is introduced to derive an inversion-free algorithm from the decision tree algorithm with the number of correctable errors less than 5. Area and timing estimates obtained by logic synthesis with 0.18 CMOS technology show that the implementation of (4359,4320)BCH (Bose-Chaud huri-Hocquenheim) decoder can achieve 248 MB/s with an estimated area of 0.31 mm2 including the embedded memory to store the received words. Compared with serial decoder, the proposed parallel architecture can achieve 8 times throughput with less than 2 times area.

Key words: parallel BCH decoder, decision tree, parallel computation of syndrome, error locator polynomial

摘要: 提出了一种用于光通信前向纠错码译码的高速并行二进制BCH(Bose-Chaudhuri-Hocquenheim)译码器的电路结构。同时提出了一种新颖的伴随式并行计算的结构,该结构面积小速度快。针对纠错位数为3的情况,基于直接求解的判决树算法,推导出一组易于硬件实现的无除法的错误位置判决多项式,该推导方法可用于纠错位数少于5的情况。基于提出的并行结构,在SIMC0.18μm的标准CMOS工艺下,实现了8位并行处理(4359,4320)BCH的译码器,结果表明在面积为0.31mm2时,时钟频率可以达到248MHz,是串行译码器数据吞吐量的8倍,而面积不到串行译码器的2倍。

关键词: 并行BCH译码器, 判决树, 并行伴随式计算, 错误位置多项式

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