Acta Scientiarum Naturalium Universitatis Pekinensis

Previous Articles     Next Articles

Capacitor-Less Fast-Response LDO for SoC Applications

SHEN Liangguo1, ZHANG Xing1, ZHAO Yuanfu2   

  1. 1. Department of Microelectronics, School of Electronics Engineering and Computer Science, Peking University, Beijing 100871; 2. Beijing Microelectronics Technology Institute, Beijing 100076;
  • Received:2007-12-09 Online:2009-01-20 Published:2009-01-20



  1. 1.北京大学信息科学技术学院微电子学系,北京100871;2.北京微电子技术研究所,北京100076;

Abstract: A low-dropout (LDO) voltage regulator with on-chip output capacitor for SoC applications is presented. The right-half-plane (RHP) zero generated by the gate-drain parasitic capacitance of the LDO pass element can be removed by a novel bi-directional asymmetric buffer (BDAB). This RHP zero removal scheme can enhance the stability, increase the unit-gain frequency (UGF) and improve the transient response performance. Post-layout simulation results of the proposed LDO show that the phase margin is better than 55°, the UGF is up to 1.7 MHz, while the overshoot and undershoot of the output voltages are less than 100 mV when the load current changes at a rate of 50 mA/μs.

Key words: voltage regulator, right-half-plane zero, capacitor-less, SoC

摘要: 提出了适合SoC应用的片上集成输出电容快速响应低压差线性稳压器(LDO)。通过使用一种新颖的双向非对称缓冲器,消除了由LDO传输元件寄生电容产生的右半平面零点。该零点的消除不仅提高了LDO的稳定性,而且可以有效拓展其单位增益带宽,从而改善瞬态响应性能。基于该缓冲器的LDO,其相位裕度大于55°,单位增益带宽可达1.7MHz,在负载电流以50mA/μs的速度阶跃变化时输出电压变化量小于100mV。

关键词: 低压差线性稳压器, 右半平面零点, 片上集成输出电容, 系统芯片

CLC Number: