Abstract: A high efficient analog charge delay line (ACDL) is proposed These analog delay lines can be used to realize high performance CMOS readout integrated circuits (ROIC) with time delay integration (TDI) function A CMOS ROIC for 288×4 IRFPA were designed, manufactured, and tested The chip has 4 video outputs, whose pixel frequency is 4-5MHz (for 384×288 format, its frame frequency can achieve 160Hz) Test results show that this chip has high dynamic range (>78dB), high linearity (>995%), and high uniformity (968%)

Key words: TDI, ROIC, analog charge delay line

摘要： 提出了一种带时间延迟积分功能的高性能CMOS读出电路芯片适用的高效率电荷延迟线结构。基于该结构，设计了一款288×4规格焦平面阵列组件适用的CMOS读出电路芯片，并已完成流片、测试。该芯片包括4个视频输出端，每个端口的像元输出频率为4～5MHz（如用于实现384×288规模的成像，帧频可达160Hz）。测试结果表明这款芯片具有高动态范围（大于78dB）、高线性度（大于995%）、高均匀性（大于968%）等特征。

关键词: TDI, 读出电路, 模拟电荷延迟线