The VLSI Implementation of Intra Prediction in H.264/AVC

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The VLSI Implementation of Intra Prediction in H.264/AVC

ZHU Zhongping¹ ， FENG Jianhua¹ ， Cao Xixin²

¹ Department of Microelectronics, Peking University,Beijing 100871； ² School of Software and Microelectronic, Peking University, Beijing 102600;

Received:2007-03-13 Online:2008-01-20 Published:2008-01-20

H.264/AVC帧内预测器的VLSI实现

朱忠平¹,冯建华¹,曹喜信²

¹ 北京大学微电子学系，北京100871；² 北京大学软件与微电子学院，北京102600；

Abstract

Abstract: An intra prediction circuit in H.264/AVC is implemented. By choosing variable circuit path and reusing adders, the authors implement all the prediction modes except plane prediction mode with low cost. Synthesized by SMIC 0.18 μm CMOS technology, the total gates is about 4000, the critical path delay is 5.7 ns.

Key words: H.264/AVC, VLSI, intra prediction

摘要： 提出了一种帧内预测电路的实现方法，在舍弃了平面预测模式情况下，通过多路选择器选择不同加法路径，和大量共用加法器，以较小代价实现了帧内预测所有剩余的预测模式。在基于SMIC CMOS 0.18 μm最坏工艺条件下，电路规模仅为4000门，关键路径延迟为5.7 ns。

关键词: H.264/AVC, VLSI, 帧内预测

CLC Number:

TP302

ZHU Zhongping,FENG Jianhua,Cao Xixin. The VLSI Implementation of Intra Prediction in H.264/AVC[J]. Acta Scientiarum Naturalium Universitatis Pekinensis.

朱忠平,冯建华,曹喜信. H.264/AVC帧内预测器的VLSI实现[J]. 北京大学学报（自然科学版）.

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URL: https://xbna.pku.edu.cn/EN/

https://xbna.pku.edu.cn/EN/Y2008/V44/I1/44

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The VLSI Implementation of Intra Prediction in H.264/AVC

H.264/AVC帧内预测器的VLSI实现

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